公开(公告)号：EP1751867A2

公开(公告)日：2007-02-14

申请号：EP05725604.2

申请日：2005-03-14

申请人： MOTOROLA INC., A Corporation of the state of Delaware

发明人： WILHITE, Jeffrey B., ,  CHARASKA, Joseph A., ,  GABATO, JR., Manuel P., ,  GAILUS, Paul H., ,  STENGEL, Robert E.,

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

摘要： A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.