摘要:
A method for measuring a voltage using a capacitive voltage divider (CVD) and an analog-to-digital converter includes the steps of measuring a bandgap or reference voltage and determining a first code value of the bandgap or reference voltage, charging a first capacitor to a voltage to be measured and determining a second code value of voltage of the first capacitor, charging a second capacitor to a second known voltage and determining a third code value of voltage of the second capacitor, and determining the voltage to be measured by applying the first, second, and third code values.
摘要:
A P-MOS transistor may be used as either a switch in a DC-DC converter or as a pass transistor of a linear regulator. When a supply voltage is above a certain voltage, the P-MOS transistor will be used in the DC-DC converter and when below the certain voltage the P-MOS transistor will be used in the linear regulator. The supply voltage may be monitored with a voltage comparator that compares the supply voltage to the certain voltage. Above the certain voltage the DC-DC converter is more efficient than the linear regulator and below the certain voltage the linear voltage regulator is more efficient than the DC-DC converter. Alternatively, selecting either the DC-DC converter or linear regulator may be done by using bonding, a jumper, a fuse link or programming a bit for different product applications during integrated circuit package fabrication or end product manufacturing.
摘要:
A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.
摘要:
A cyclical pulsing oscillator having a pulse repetition rate close to a crystal resonant frequency in an oscillator provides more useful start-up energy to the crystal oscillator circuit and thus provides much faster start-up time. The start-up pulsing oscillator runs for a number of cycles or until the crystal oscillator amplitude as built up to a desired value. The pulsing oscillator may have a repetition rate of from about one-third to about one-half the crystal resonant frequency, thus providing more useful start-up energy to the crystal oscillator circuit.
摘要:
A crystal oscillator is started in a high power mode for a certain period of time to ensure starting oscillation with average grade crystals, then once the certain time period is over the oscillator switches into a low power mode and sustains oscillation with energy pulses triggered by and synchronized with the oscillator output frequency. These energy pulses may be generated on the positive, negative or both positive and negative edges of the clock output waveform.