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公开(公告)号：EP3683967A1
公开(公告)日：2020-07-22
申请号：EP17929219.8
申请日：2017-10-17
发明人： WADA, Osamu , MIZUTANI, Hiroyuki , TAJIMA, Kenichi
摘要： Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source.
A signal source of the present invention includes: a reference signal source for outputting a reference signal; a phase frequency comparator for detecting a phase difference between the reference signal and an oscillation signal and outputting a signal corresponding to the phase difference; a filter for filtering the signal output by the phase frequency comparator; an oscillator for outputting the oscillation signal depending on the signal filtered by the filter; and an S/H circuit for receiving a clock signal for controlling a phase of the oscillation signal by controlling sampling operation and holding operation, sampling at least one of the oscillation signal and the reference signal in synchronization with the clock signal, and outputting at least one of the sampled reference signal and the sampled oscillation signal to the phase frequency comparator, the S/H circuit disposed between the oscillator and the phase frequency comparator or between the reference signal source and the phase frequency comparator.-
公开(公告)号：EP4033257A1
公开(公告)日：2022-07-27
申请号：EP19954372.9
申请日：2019-11-26
发明人： WADA, Osamu , NAKAMIZO, Hideyuki
IPC分类号： G01R23/12
摘要： A frequency detection circuit (3) includes a signal source (11) that outputs a first clock signal and a second clock signal that has the same frequency as the first clock signal and a different phase from the first clock signal, a S/H circuit (12) that undersamples a frequency-detection target signal using the first clock signal output from the signal source (11) and outputs a first sampling signal indicating a result of undersampling, and undersamples the frequency-detection target signal using the second clock signal output from the signal source (11) and outputs a second sampling signal indicating a result of undersampling, and a frequency calculation circuit (14) that calculates a phase difference between the first sampling signal output from the S/H circuit (12) and the second sampling signal output from the S/H circuit (12) and calculates the frequency of the frequency-detection target signal on the basis of the phase difference.
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公开(公告)号：EP3780908A1
公开(公告)日：2021-02-17
申请号：EP18919096.0
申请日：2018-05-15
发明人： HIRAI, Akihito , KUWATA, Eigo , WADA, Osamu , IYOMASA, Kazuhiro
IPC分类号： H05B6/48
摘要： What is provided are: two or more electrodes (10a, 10b); a grounded surface (3) connected to one of the electrodes (10b); a signal source (2) that is connected to one of the electrodes (10a) other than the electrode connected to the grounded surface (3), and that outputs a high-frequency signal; a high-frequency passing heat-insulation element (11a) that is interposed serially between the signal source (2) and the electrode (10a) connected to the signal source (2), and that causes the high-frequency signal outputted from the signal source (2) to pass therethrough, by using electric coupling or magnetic coupling between two terminals (i, ii) in the element that are not connected to each other by metal; and a high-frequency passing heat-insulation element (11b) that is interposed serially between the grounded surface (3) and the electrode (10b) connected to the grounded surface (3), and that, by using electric coupling between two terminals (i, ii) therein, outputs the high-frequency signal outputted from the signal source (2), to the grounded surface (3).
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公开(公告)号：EP3896465A1
公开(公告)日：2021-10-20
申请号：EP19911540.3
申请日：2019-01-22
发明人： WADA, Osamu , TAJIMA, Kenichi
摘要： Conventional frequency detection circuits have a disadvantage that the circuit scale increases as the frequency of a reception signal to be detected increases.
A frequency detection circuit of the present invention includes: a first signal source for outputting a first clock signal; a second signal source for outputting a second clock signal having the same frequency as but a different phase from those of the first clock signal; a first sample hold circuit for undersampling a reception signal using the first clock signal; a second sample hold circuit for undersampling the reception signal using the second clock signal; and a frequency calculating circuit for calculating the frequency of the reception signal using a phase difference between output signals of the first sample hold circuit and the second sample hold circuit.
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