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    Logic circuit
    1.
    发明公开
    Logic circuit 失效

    公开(公告)号：EP0219867A2

    公开(公告)日：1987-04-29

    申请号：EP86114694.2

    申请日：1986-10-23

    申请人： NEC CORPORATION

    发明人： Dasai, Teiji ,  Hiki, Yoshimasa

    IPC分类号： H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K19/0136

    摘要： A current-mode logic circuit includes a pair of input bipolar transistors (16, 36) coupled in the emitter-coupled single differential circuit configuration, one (16) of which input transistors is connected at its base to receive an input signal and the other input transistor (36) is connected at its base to receive a reference voltage. The collector of each of the input transistor is connected to a base of an emitter-follower driver (42, 44) which is in turn connected at its collector to a voltage supply terminal (20) and at its emitter through load means to another voltage supply terminal (50). The emitters of these output transistors are connected to a pair of output terminals (52, 54) to generate a pair of complementary logic signals. Further, there are provided first and second auxiliary transistors (60, 12) connected in the cross-coupled flip-flop configuration and connected at their collectors to the emitters of the first and second output bipolar transistors (42, 44), respectively.

    Logic circuit
    3.
    发明公开
    Logic circuit 失效
    逻辑电路

    公开(公告)号：EP0219867A3

    公开(公告)日：1987-12-23

    申请号：EP86114694

    申请日：1986-10-23

    申请人： NEC CORPORATION

    发明人： Dasai, Teiji ,  Hiki, Yoshimasa

    IPC分类号： H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K19/0136

    摘要： A current-mode logic circuit includes a pair of input bipolar transistors (16, 36) coupled in the emitter-coupled single differential circuit configuration, one (16) of which input transistors is connected at its base to receive an input signal and the other input transistor (36) is connected at its base to receive a reference voltage. The collector of each of the input transistor is connected to a base of an emitter-follower driver (42, 44) which is in turn connected at its collector to a voltage supply terminal (20) and at its emitter through load means to another voltage supply terminal (50). The emitters of these output transistors are connected to a pair of output terminals (52, 54) to generate a pair of complementary logic signals. Further, there are provided first and second auxiliary transistors (60, 12) connected in the cross-coupled flip-flop configuration and connected at their collectors to the emitters of the first and second output bipolar transistors (42, 44), respectively.

    摘要翻译： 电流模式逻辑电路包括以发射极耦合单差分电路配置耦合的一对输入双极晶体管（16,36），其中一个（16）的输入晶体管在其基极连接以接收输入信号，而另一个 输入晶体管（36）在其基极连接以接收参考电压。 每个输入晶体管的集电极连接到发射极跟随器驱动器（42,44）的基极，该发射极跟随器驱动器依次在其集电极连接到电压供应端子（20）并且在其发射极通过负载装置连接到另一个电压 供电端子（50）。 这些输出晶体管的发射极连接到一对输出端子（52,54）以产生一对互补的逻辑信号。 此外，提供了以交叉耦合的触发器配置连接的第一和第二辅助晶体管（60,12），并且它们的集电极分别连接到第一和第二输出双极晶体管（42,44）的发射极。