公开(公告)号：EP2060924B1

公开(公告)日：2013-10-23

申请号：EP07792273.0

申请日：2007-08-09

申请人： NEC Corporation

发明人： MIZUNO, Masayuki ,  NAKURA, Toru ,  NOSE, Koichi

IPC分类号： G06F11/277 ,  G06F11/22 ,  G01R31/317 ,  G01R31/3193

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/31937

公开(公告)号：EP2060924A1

公开(公告)日：2009-05-20

申请号：EP07792273.0

申请日：2007-08-09

申请人： NEC Corporation

发明人： MIZUNO, Masayuki ,  NAKURA, Toru ,  NOSE, Koichi

IPC分类号： G01R31/28 ,  G06F11/22

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/31937

摘要： The present invention provides a synchronous-type semiconductor integrated circuit with high reliability. In the semiconductor integrated circuit, a delay circuit is connected to a data line. The semiconductor integrated circuit includes a first storage circuit 101 and a second storage circuit 102 that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit 104 that determines whether or not the results of the first storage circuit 101 and the second storage circuit 102 coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

摘要翻译： 本发明提供一种高可靠性的同步型半导体集成电路。 在半导体集成电路中，延迟电路连接到数据线。 半导体集成电路包括：第一存储电路101和第二存储电路102，分别存储延迟电路的输入的逻辑电平和时钟线的逻辑电平改变时延迟电路的输出，以及确定电路 104，其确定第一存储电路101和第二存储电路102的结果是否一致。 即使构成半导体集成电路的晶体管或布线由于长期变化等而降级，也可以在异常或异常之前预测由劣化引起的运算电路之一的异常或故障的可能性 发生故障

公开(公告)号：EP2103948A1

公开(公告)日：2009-09-23

申请号：EP07850815.7

申请日：2007-12-18

申请人： NEC Corporation

发明人： NOSE, Koichi ,  MIZUNO, Masayuki

IPC分类号： G01R19/00 ,  G01R23/16

CPC分类号： H04B17/318 ,  G01R23/16 ,  H04B17/15

摘要： In the signal quality measurement device of the present invention, a spectrum measurement circuit (101) includes: an N-(where N is an integer equal or greater than 2) phase clock generation circuit (304) for supplying phase-modulated signals in which the phase of a clock signal is shifted by a phase modulation amount each time the settings of the phase modulation amount are switched; a mixer circuit (303) for taking the product of a measured signal that is supplied from a transmitter and the phase-modulated signals that are supplied from the N-phase clock generation circuit (304); an average value output circuit (305) for supplying an average voltage value of the output signal of the mixer circuit (303); a memory (307) for storing the average voltage value supplied from the average value output circuit (305) for each phase modulation amount of the N-phase clock generation circuit (304); and arithmetic unit (308) for using the average voltage value for each phase modulation amount of the N-phase clock generation circuit (304) that is stored in memory (307) to calculate the signal strength of the measured signal.

摘要翻译： 在本发明的信号质量测量装置中，频谱测量电路（101）包括：N（其中N是等于或大于2的整数）相位时钟产生电路（304），用于提供相位调制信号，其中 每当切换相位调制量的设定时，时钟信号的相位偏移相位调制量; 用于获取从发送器提供的测量信号和从N相时钟产生电路（304）提供的相位调制信号的乘积的混频器电路（303）; 平均值输出电路（305），用于提供混频电路（303）的输出信号的平均电压值; 存储从所述平均值输出电路（305）提供的平均电压值用于所述N相时钟发生电路（304）的每个相位调制量的存储器（307）。 和运算单元（308），用于对存储在存储器（307）中的N相时钟产生电路（304）的每个相位调制量的平均电压值进行计算，以计算测量信号的信号强度。

公开(公告)号：EP2166719A1

公开(公告)日：2010-03-24

申请号：EP08765276.4

申请日：2008-06-06

申请人： Nec Corporation

发明人： NOSE, Koichi ,  ISHIZAKI, Haruya ,  MIZUNO, Masayuki

IPC分类号： H04L27/12

CPC分类号： H04L27/20 ,  H03K5/13 ,  H03K5/156 ,  H03K2005/00052 ,  H04L27/12

摘要： Provided is a modulation device including a signal selection circuit selecting two carrier signals from a plurality of carrier signals having the same frequency and the same phase difference according to a defined control signal and outputting the selected carrier signals, and a phase interpolator adjusting the phase in smaller units than the phase difference between the plurality of carrier signals according to the control signal and modulating the frequency or the phase of the carrier signal into a baseband signal based on the carrier signals selected by the signal selection circuit to generate a carrier wave signal.

摘要翻译： 提供了一种调制装置，其包括：信号选择电路，根据定义的控制信号从具有相同频率和相同相位差的多个载波信号中选择两个载波信号并输出​​所选择的载波信号;以及相位内插器， 根据控制信号比多个载波信号之间的相位差小的单位，并且基于由信号选择电路选择的载波信号将载波信号的频率或相位调制为基带信号，以产生载波信号。

公开(公告)号：EP2063531A1

公开(公告)日：2009-05-27

申请号：EP07807243.6

申请日：2007-09-13

申请人： NEC Corporation

发明人： NOSE, Koichi ,  ISHIZAKI, Haruya ,  MIZUNO, Masayuki

IPC分类号： H03K4/02 ,  H03F3/24 ,  H03F3/68 ,  H03K4/92 ,  H03K5/02

CPC分类号： H03K4/026 ,  H03F1/0294 ,  H03F1/32 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/384 ,  H03K4/92

摘要： [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. [MEANS FOR SOLVING THE PROBLEMS] The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

摘要翻译： 为了提供例如能够以低电压和低功率工作的脉冲输入型功率放大装置，能有效地抑制谐波分量的产生。 解决问题的手段放大装置包括至少两个放大电路，一个放大电路和另一个放大电路，其输出侧相互连接并以相同频率驱动的多个放大器组成。 形成一个放大电路的多个放大器配置有输入和放大参考脉冲的第一反相放大器M12和输入通过移位和反相参考脉冲的相位形成的反相脉冲的第二反相放大器M11。 另一个放大电路配置有第一反相放大器M14和第二反相放大器M13，其中通常输入宽度大于参考脉冲宽度的其它宽脉冲。