公开(公告)号：EP1601103A1

公开(公告)日：2005-11-30

申请号：EP04717309.1

申请日：2004-03-04

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： OTOMO, Yusuke, Ntt Intellectual Property Center ,  NOGAWA, Masafumi, Ntt Intellectual Property Center

IPC分类号： H03K5/26 ,  H04L7/033 ,  H03L7/08

CPC分类号： H03L7/0893 ,  H03L7/0895 ,  H03L7/091 ,  H04L7/033

摘要： Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock signal whose period is 2 times the unit time width of the inputted data signal, the pulse width of the phase error signal, representing the difference in phase between the transition point of the data signal and the transition point of the clock signal, is extended as much as the unit time width of the data signal.

摘要翻译： 通过降低相位比较器电路的运行速度，提供具有稳定时钟提取功能的CDR电路和具有高速数据输入处理的数据再生功能。 利用能够以输入数据信号的单位时间宽度的2倍的时钟信号进行工作的相位比较器电路，相位误差信号的脉冲宽度表示数据信号的转变点与 时钟信号的转换点与数据信号的单位时间宽度一样扩展。

公开(公告)号：EP1601103B1

公开(公告)日：2012-02-29

申请号：EP04717309.1

申请日：2004-03-04

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： OTOMO, Yusuke, Ntt Intellectual Property Center ,  NOGAWA, Masafumi, Ntt Intellectual Property Center

IPC分类号： H03K5/26 ,  H04L7/033 ,  H03L7/08 ,  H03L7/091

CPC分类号： H03L7/0893 ,  H03L7/0895 ,  H03L7/091 ,  H04L7/033

摘要： There is provided a CDR circuit mitigating operation speed of a phase comparison circuit and having a stable clock extraction function and data rectifying function even for a high-speed data signal input. The phase comparison circuit operates by a clock signal having a cycle twice as long as a unit time width of the data signal input. In this phase comparison circuit, a phase error signal pulse width indicating the phase difference between the data signal transient point and the clock signal transient point is prolonged by the unit time width of the data signal.