公开(公告)号：EP0492869A2

公开(公告)日：1992-07-01

申请号：EP91311388.2

申请日：1991-12-06

申请人： NORTHERN TELECOM LIMITED

发明人： Mayo, Richard Hamond ,  Tipper, Alan

IPC分类号： H04L7/033

CPC分类号： H04L7/033

摘要： A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131), connected in cascade, means for applying digital data signals to the first latch, means for clocking (701) the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means (201) to which are applied the digital data signal (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X = B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch.

摘要翻译： 一种数字信号数据重定时和时钟提取装置，包括串联连接的一系列三个数据锁存器（111,121,131），用于将数字数据信号施加到第一锁存器的装置，用于对第一和第三锁存器 与输入到第一锁存器的数据信号同相，用于与输入到第一锁存器的数据信号相反地对第二锁存器进行计时的装置，将输入到第一锁存器的数字数据信号（A）施加到其上的符合检测装置（201） 第一锁存器，第二锁存器的数据信号输出（B）和第三锁存器的数据信号输出（C），重合检测装置被安排成根据算法X = B导出输出数据信号（X）。 （AC）和第一锁相环反馈装置（Q1，Q2,301），由此一致检测电路的输出数据信号（X）控制时钟装置的定时，以保持与数字数据信号输入的相位关系 到第一 锁存器。

公开(公告)号：EP0492869B1

公开(公告)日：1996-01-03

申请号：EP91311388.2

申请日：1991-12-06

申请人： NORTHERN TELECOM LIMITED

发明人： Mayo, Richard Hamond ,  Tipper, Alan

IPC分类号： H04L7/033

CPC分类号： H04L7/033

公开(公告)号：EP0492869A3

公开(公告)日：1992-12-02

申请号：EP91311388.2

申请日：1991-12-06

申请人： NORTHERN TELECOM LIMITED

发明人： Mayo, Richard Hamond ,  Tipper, Alan

IPC分类号： H04L7/033

CPC分类号： H04L7/033

摘要： A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131), connected in cascade, means for applying digital data signals to the first latch, means for clocking (701) the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means (201) to which are applied the digital data signal (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X = B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch.