A method and apparatus for phase detection in digital signals
    1.
    发明公开
    A method and apparatus for phase detection in digital signals 失效
    在Phasendetektieren数字信号的方法和装置

    公开(公告)号:EP0874449A3

    公开(公告)日:1999-11-10

    申请号:EP98303144.4

    申请日:1998-04-23

    IPC分类号: H03D13/00

    CPC分类号: H04L7/033 G01R25/00 H03L7/085

    摘要: The invention seeks to provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, the present invention avoids a source of non-linearity exhibited in existing phase detectors. In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation. The present invention also seeks to provide an improved digital signal threshold detector and a digital signal regenerator based on said apparatus.

    A method and apparatus for phase detection in digital signals
    2.
    发明公开
    A method and apparatus for phase detection in digital signals 失效
    Verfahren undGerätzum Phasendetektieren在digitale Signalen

    公开(公告)号:EP0874449A2

    公开(公告)日:1998-10-28

    申请号:EP98303144.4

    申请日:1998-04-23

    IPC分类号: H03D13/00

    CPC分类号: H04L7/033 G01R25/00 H03L7/085

    摘要: The invention seeks to provide an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, the present invention avoids a source of non-linearity exhibited in existing phase detectors.
    In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation.
    The present invention also seeks to provide an improved digital signal threshold detector and a digital signal regenerator based on said apparatus.

    摘要翻译: 本发明寻求提供一种用于检测数字数据信号和时钟信号之间的相位差的改进的方法和装置。 通过确保输出相位信号中的脉冲没有足够窄以引入非线性,本发明避免了现有相位检测器中出现的非线性源。 此外,通过确保通过电路的关键定时路径包含类似的电路块,具有相似的传播延迟,相对时间关系从时钟和数据输入保留到异或输入。 因此,只要它们一起移动,就像在集成电路实现中一样,电路对组件特性的变化很大程度上不敏感。 本发明还寻求提供一种基于所述装置的改进的数字信号阈值检测器和数字信号再生器。