公开(公告)号：EP3618284A1

公开(公告)日：2020-03-04

申请号：EP18192120.6

申请日：2018-08-31

申请人： NXP B.V.

发明人： Fan,, Hao ,  Pertijs,, Michiel ,  Buter,, Berry

IPC分类号： H03M1/14 ,  H03M1/10 ,  H03M1/50 ,  H03M1/54

摘要： A capacitance-to-digital-converter comprising: a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.