公开(公告)号：EP2330730B1

公开(公告)日：2014-07-02

申请号：EP09178092.4

申请日：2009-12-04

申请人： NXP B.V.

发明人： Kuebrich, Johann Baptist Daniel ,  Schmid, Markus ,  Duerbaum, Thomas Antonius ,  Pansier, Frans ,  Hoogzaad, Gian ,  Halberstadt, Hans

IPC分类号： H02M3/335 ,  H03K5/1532 ,  H03K5/1536 ,  H03K17/13

CPC分类号： H03K5/1532 ,  H02M3/33592 ,  H03K5/1536 ,  H03K17/133 ,  Y02B70/1475

公开(公告)号：EP2538231A1

公开(公告)日：2012-12-26

申请号：EP11250604.3

申请日：2011-06-22

申请人： NXP B.V.

发明人： Stahl, Juergen ,  Pawellek, Alexander ,  Schmid, Markus ,  Duerbaum, Thomas Antonius ,  Kuebrich, Johann Baptist Daniel ,  Halberstadt, Hans ,  Pansier, Frans

IPC分类号： G01R31/00

CPC分类号： G01R29/26 ,  G01R31/001 ,  G01R31/40

摘要： The present invention relates to a noise sensor for an alternating or direct current power supply. The sensor comprises a noise sensing unit and a noise separator. The noise separator is configured to receive first and second input signals and provide a first output signal representative of the common mode noise and a second output signal representative of the differential mode noise. The noise sensing unit comprises a first capacitive element that couples the first input of the noise separator to a first power terminal and a second capacitive element that couples the second input of the noise separator to a second power terminal.

摘要翻译： 本发明涉及用于交流或直流电源的噪声传感器。 传感器包括噪声感测单元和噪声分离器。 噪声分离器被配置为接收第一和第二输入信号并且提供表示共模噪声的第一输出信号和表示差模噪声的第二输出信号。 噪声感测单元包括将噪声分离器的第一输入端耦合到第一电源端子的第一电容元件和将噪声分离器的第二输入端耦合到第二电源端子的第二电容元件。

公开(公告)号：EP2375553A1

公开(公告)日：2011-10-12

申请号：EP09252937.9

申请日：2009-12-31

申请人： NXP B.V.

发明人： Schmid, Markus ,  Kuebrich, Johann Baptist Daniel ,  Duerbaum, Thomas Antonius ,  Hoogzaad, Gian ,  Laro, Peter ,  Pansier, Frans

IPC分类号： H02M1/42

CPC分类号： H02M1/4208 ,  Y02B70/126

摘要： A circuit comprising a power factor correction stage (400') having a DC input, a ground input, a DC output and a ground output; a capacitor (430'; 430"'); a diode (426'; 426"'); and discharge means (432'; 432"'). A first terminal of the diode (426'; 426"') is connected to an input of the power factor correction stage, a second terminal of the diode (426'; 426"') is connected to the first plate of the capacitor (430'; 430"'); and the second plate of the capacitor (430'; 430'") is connected to the other input of the PFC stage. The discharge means (432'; 432"') is connected to the capacitor (430'; 430"') and is configured to discharge the capacitor such that it contributes to the output of the PFC stage when the level of a signal at the input of the PFC stage falls below a threshold value.

摘要翻译： 包括具有DC输入，接地输入，DC输出和接地输出的功率因数校正级（400'）的电路; 电容器（430'; 430“'）;二极管（426'; 426”'）; 二极管（426'; 426“'）的第一端子连接到功率因数校正级的输入端，二极管的第二端子（426'; 426”'）连接到功率因数校正级的输入端， '）连接到电容器（430'; 430“'）的第一板上; 并且所述电容器（430'; 430“”）的第二板连接到所述PFC级的另一输入端，所述放电装置（432'; 432“'）连接到所述电容器（430'; 430”'） 并且被配置为放电电容器，使得当PFC级的输入端的信号电平低于阈值时，它有助于PFC级的输出。

公开(公告)号：EP2360820A1

公开(公告)日：2011-08-24

申请号：EP09252933.8

申请日：2009-12-31

申请人： NXP B.V.

发明人： Schmid, Markus ,  Kuebrich, Johann Baptist Daniel ,  Duerbaum, Thomas Antonius ,  Hoogzaad, Gian ,  Laro, Peter ,  Pansier, Frans

IPC分类号： H02M1/42

CPC分类号： H02M1/4208 ,  Y02B70/126

摘要： A surge protection circuit for a circuit comprising a rectification module (433). The surge protection circuit comprising a first diode (420), a second diode (422), a capacitor (424; 524; 624) and discharge means (426). The anode of the first diode (420) is connected to a first input of the rectification module (433), and the anode of the second diode (422) is connected to a second input of the rectification module (433). The cathode of the first and second diodes (420, 422) are both connected to the first plate of the capacitor (424; 524; 624). The second plate of the capacitor (424; 524; 624) is connected to the negative output of the rectification module (433). The capacitor (424; 524; 624) is configured such that it is consistently charged to substantially the peak value of a supply voltage during normal operation between surge events. The discharge means (426) is connected to the first plate of the capacitor (424; 524; 624) and is configured to discharge the capacitor (424; 524; 624) when the voltage across the capacitor (424; 524; 624) is in excess of the peak of the maximum value of the normal supply voltage and not discharge the capacitor when the voltage across the capacitor is not in excess of the peak of the maximum value of the normal supply voltage.

摘要翻译： 一种用于包括整流模块（433）的电路的浪涌保护电路。 浪涌保护电路包括第一二极管（420），第二二极管（422），电容器（424; 524; 624）和放电装置（426）。 第一二极管（420）的阳极连接到整流模块（433）的第一输入端，第二二极管（422）的阳极连接到整流模块（433）的第二输入端。 第一和第二二极管（420,422）的阴极都连接到电容器（424; 524; 624）的第一板。 电容器（424; 524; 624）的第二板连接到整流模块（433）的负极输出端。 电容器（424; 524; 624）被配置为使得其在浪涌事件之间的正常操作期间一直被充电到基本上电源电压的峰值。 放电装置（426）连接到电容器（424; 524; 624）的第一板上，并且当电容器（424; 524; 624）两端的电压为 超过正常电源电压的最大值的峰值，并且当电容器两端的电压不超过正常电源电压的最大值的峰值时，不对电容器放电。

公开(公告)号：EP2315497A1

公开(公告)日：2011-04-27

申请号：EP09252396.8

申请日：2009-10-09

申请人： NXP B.V.

发明人： Schmid, Markus ,  Kuebrich, Johann Baptist Daniel ,  Duerbaum, Thomas Antonius ,  Pansier, Frans ,  Halberstadt, Hans ,  Hoogzaad, Gian

IPC分类号： H05B33/08 ,  H02M1/42

CPC分类号： H05B33/0815 ,  H02M1/4225 ,  H02M2001/007 ,  H05B33/0827 ,  Y02B70/126

摘要： A driver circuit (602) for one or more light emitting diodes (618) comprising a controllable power factor correction circuit (610) configured to receive a rectified alternating voltage and generate a PFC output voltage (612), and a linear regulator (616) configured to receive the PFC output voltage (612) and a current mode control signal (626), and generate an LED driver output voltage (620) with a substantially constant current in accordance with the current mode control signal (626). The driver circuit (602) further comprising a headroom control component (616) configured to generate a headroom control signal (608) representative of an excess voltage. The controllable power factor correction circuit (610) is configured to receive the headroom control signal (608) and adjust one or more parameters of the power factor correction circuit (610) in accordance with the headroom control signal (608) in order to adjust the PFC output voltage (612).

摘要翻译： 一种用于一个或多个发光二极管（618）的驱动器电路（602），包括被配置为接收经整流的交流电压并产生PFC输出电压（612）的可控功率因数校正电路（610），以及线性调节器（616） 被配置为接收PFC输出电压（612）和电流模式控制信号（626），并且根据电流模式控制信号（626）产生具有基本恒定电流的LED驱动器输出电压（620）。 驱动器电路（602）还包括余热控制部件（616），其被配置为产生代表过电压的裕量控制信号（608）。 可控功率因数校正电路（610）被配置为接收余量控制信号（608），并且根据余量控制信号（608）调整功率因数校正电路（610）的一个或多个参数，以便调整 PFC输出电压（612）。

公开(公告)号：EP2360820B1

公开(公告)日：2018-03-28

申请号：EP09252933.8

申请日：2009-12-31

申请人： NXP B.V.

发明人： Schmid, Markus ,  Kuebrich, Johann Baptist Daniel ,  Duerbaum, Thomas Antonius ,  Hoogzaad, Gian ,  Laro, Peter ,  Pansier, Frans

IPC分类号： H02M1/42

CPC分类号： H02M1/4208 ,  Y02B70/126

摘要： A surge protection circuit for a circuit comprising a rectification module (433). The surge protection circuit comprising a first diode (420), a second diode (422), a capacitor (424; 524; 624) and discharge means (426). The anode of the first diode (420) is connected to a first input of the rectification module (433), and the anode of the second diode (422) is connected to a second input of the rectification module (433). The cathode of the first and second diodes (420, 422) are both connected to the first plate of the capacitor (424; 524; 624). The second plate of the capacitor (424; 524; 624) is connected to the negative output of the rectification module (433). The capacitor (424; 524; 624) is configured such that it is consistently charged to substantially the peak value of a supply voltage during normal operation between surge events. The discharge means (426) is connected to the first plate of the capacitor (424; 524; 624) and is configured to discharge the capacitor (424; 524; 624) when the voltage across the capacitor (424; 524; 624) is in excess of the peak of the maximum value of the normal supply voltage and not discharge the capacitor when the voltage across the capacitor is not in excess of the peak of the maximum value of the normal supply voltage.

公开(公告)号：EP2341605A3

公开(公告)日：2011-12-07

申请号：EP09252935.3

申请日：2009-12-31

申请人： NXP B.V.

发明人： Pansier, Frans ,  Duerbaum, Thomas Antonius ,  Schmid, Markus ,  Mühlbauer, Klaus ,  Kuebrich, Johann Baptist Daniel

IPC分类号： H02M3/158 ,  H02M1/42

CPC分类号： H02M3/1584 ,  H02M1/4225 ,  Y02B70/126

摘要： A power factor correction stage comprising: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a first converter stage and one or more further converter stages, wherein each of the converter stages is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and a controller configured to operate the switches of the converter stages. The controller is configured to operate the switch of the one or more further converter stages at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time corresponds to a proportion of the switching frequency for an earlier switching cycle that does not correspond to substantially the period of the earlier switching cycle divided by the number of converter stages.

摘要翻译： 一种功率因数校正级，包括：被配置为接收输入信号的输入端; 输出端子，被配置为提供输出信号; 第一转换器级和一个或多个其它转换器级，其中每个转换器级连接到输入端和输出端，并且每个转换级包括开关; 以及控制器，被配置为操作所述转换器级的开关。 控制器被配置为在当前开关周期的第一转换器级的开关操作之后的一段时间内操作一个或多个其它转换器级的开关，其中该时间段对应于开关频率的比例 对于较早的开关周期，其基本上不对应于较早开关周期的周期除以转换器级的数量。

公开(公告)号：EP2341605A2

公开(公告)日：2011-07-06

申请号：EP09252935.3

申请日：2009-12-31

申请人： NXP B.V.

发明人： Pansier, Frans ,  Duerbaum, Thomas Antonius ,  Schmid, Markus ,  Mühlbauer, Klaus ,  Kuebrich, Johann Baptist Daniel

IPC分类号： H02M3/158 ,  H02M1/42

CPC分类号： H02M3/1584 ,  H02M1/4225 ,  Y02B70/126

摘要： A power factor correction stage comprising: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a first converter stage and one or more further converter stages, wherein each of the converter stages is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and a controller configured to operate the switches of the converter stages. The controller is configured to operate the switch of the one or more further converter stages at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time corresponds to a proportion of the switching frequency for an earlier switching cycle that does not correspond to substantially the period of the earlier switching cycle divided by the number of converter stages.

摘要翻译： 一种功率因数校正级，包括：输入端，被配置为接收输入信号; 输出端子，被配置为提供输出信号; 第一转换器级和一个或多个另外的转换器级，其中每个转换器级连接到输入端子和输出端子，并且每个转换器级包括开关; 以及配置成操作转换器级的开关的控制器。 控制器被配置为在第一转换器级的开关操作之后的一段时间内操作一个或多个另外的转换器级的开关用于电流开关周期，其中该时间段对应于开关频率的一部分 用于较早的开关周期，其基本上不对应于较早的开关周期的周期除以转换器级的数量。

公开(公告)号：EP2568588A1

公开(公告)日：2013-03-13

申请号：EP11180398.7

申请日：2011-09-07

申请人： NXP B.V.

发明人： Schmid, Markus ,  Kuebrich, Johann Baptist ,  Duerbaum, Thomas ,  Halberstadt, Hans ,  Hoogzaad, Gian ,  Pansier, Frans

IPC分类号： H02M3/335

CPC分类号： H02M3/33507 ,  H02M1/08 ,  H02M3/33523 ,  H02M2001/0032 ,  H02M2001/0035 ,  H02M2001/0054 ,  H02M2001/0058 ,  Y02B70/1491 ,  Y02B70/16

摘要： A method is disclosed of controlling a switched mode converter comprising a switch and for providing power to device having a load, comprising: in response to the load exceeding a first threshold, operating in a first mode, being a CCM; in response to the load exceeding a second threshold and not exceeding the first threshold, operating in second mode, being a BCM without valley skipping wherein the switching frequency increases with decreasing load; in response to the load exceeding a third threshold and not exceeding the second threshold, operating in a third mode, being a BCM with valley skipping, wherein the switching frequency depends on the load and the number of valleys skipped and is between a fixed upper and a lower switching frequency limit; and in response to the load not exceeding the third threshold, operating in a fourth mode, being a BCM with valley skipping, wherein the switching frequency depends on at least the load, and is between an upper and a lower switching frequency limit wherein the upper switching frequency limit decreases with decreasing load.
A switched mode converter controlled by such a method is also disclosed.

摘要翻译： 公开了一种控制包括开关并用于向具有负载的装置提供电力的开关模式转换器的方法，包括：响应于所述负载超过第一阈值，以第一模式操作，为CCM; 响应于所述负载超过第二阈值并且不超过所述第一阈值，以第二模式操作，作为不具有谷跳越的BCM，其中所述开关频率随负载减小而增加; 响应于超过第三阈值并且不超过第二阈值的负载，在第三模式中操作，作为具有谷跳跃的BCM，其中开关频率取决于跳过的负载和谷数，并且在固定的上限和 较低的开关频率限制; 并且响应于不超过第三阈值的负载，以第四模式操作，作为具有谷跳跃的BCM，其中开关频率至少取决于负载，并且处于上和下开关频率极限之间，其中上部 开关频率限制随负载减小而减小。 还公开了通过这种方法控制的开关模式转换器。

公开(公告)号：EP2365624A1

公开(公告)日：2011-09-14

申请号：EP10156424.3

申请日：2010-03-12

申请人： NXP B.V.

发明人： Duerbaum, Thomas Antonius ,  Kuebrich, Johann Baptist Daniel ,  Schmid, Markus ,  Hoogzaad, Gian ,  Halberstadt, Hans ,  Pansier, Frans

IPC分类号： H02M3/335

CPC分类号： H02M3/33507

摘要： Embodiments of the present invention relate to a power conversion system, in particular a switched mode power supply, SMPS, which comprises a control circuit and a rectifier circuit connectable to an alternating main power supply. The rectifier circuit is directly connected to the control circuit for supplying the control circuit with rectified power. The power conversion system further comprises a start-up circuit having a supply capacitor which is connected to the control circuit for providing a start-up voltage, and further to the rectifier circuit.

摘要翻译： 本发明的实施例涉及一种功率转换系统，特别是开关模式电源SMPS，其包括可连接到交替主电源的控制电路和整流器电路。 整流电路直接连接到控制电路，为控制电路提供整流电源。 电力转换系统还包括启动电路，该启动电路具有连接到用于提供启动电压的控制电路的供电电容，并且还包括整流电路。