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公开(公告)号：EP4350383A1
公开(公告)日：2024-04-10
申请号：EP23201290.6
申请日：2023-10-02
申请人： NXP B.V.
发明人： Schneider, Tobias , Pimentel de Alvarenga, Eduardo , Medwed, Marcel , Kraft, Erik , Lemsitzer, Stefan , Spreitzer, Robert
摘要： A method is provided for detecting interference in a radar system. The method includes transmitting, by a transmitter of the radar system, a sequence of radar pulses at a regular interval with a rest period following each radar pulse of the sequence of radar pulses. The transmitter is disabled during each rest period. A receiver is enabled to receive reflected radar pulses from a target during the rest period following each radar pulse of the sequence of radar pulses. Some of the radar pulses are selected to be omitted and not transmitted. The receiver is still enabled during the rest periods following the omitted transmission pulses. Any reflected pulses received during the rest periods following the omitted transmission pulses may be an indication of a targeted interference of the radar system. In another embodiment, a radar system is provided.
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公开(公告)号：EP4287055A1
公开(公告)日：2023-12-06
申请号：EP23175698.2
申请日：2023-05-26
申请人： NXP B.V.
摘要： One example securely updates an integrated circuit to mitigate undesirable modifications and this involves an application circuit accessing an external network while a (e.g., nonvolatile) program memory is write protected; and a reset-boot circuit resetting and booting the application circuit while access to the external network is disabled, and causing an update for the application circuit. In response to an indication that an update is downloaded for installation, the downloaded update is installed in the memory while access to the external network is disabled, and execution of the reset mode is permitted after the update is installed. Also, a retrieval module may download, in response to an indication that an update is not downloaded, an update provided via the external network while the memory is write-protected and thereby permitting execution of the reset mode after the update is downloaded.
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公开(公告)号：EP4387156A1
公开(公告)日：2024-06-19
申请号：EP23214876.7
申请日：2023-12-07
申请人： NXP B.V.
CPC分类号： H04L9/004 , H04L9/3093
摘要： Various embodiments relate to a fault detection system and method for polynomial operations, including: selecting a plurality of evaluation points; evaluating a first polynomial at the plurality of evaluation points to produce first results; applying a first function to the first polynomial to produce a second polynomial; evaluating the second polynomial at the plurality of evaluation points second results; evaluating a second scalar function on the first results to produce third results; comparing the second results to the third results; and performing a polynomial operation using the second polynomial when the second results match the third results.
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公开(公告)号：EP4287556A1
公开(公告)日：2023-12-06
申请号：EP23176177.6
申请日：2023-05-30
申请人： NXP B.V.
IPC分类号： H04L9/30
摘要： Various implementations relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including a masked decomposition of a polynomial a having n s arithmetic shares into a high part a 1 and a low part a 0 for lattice-based cryptography in a processor, the instructions, including: performing a rounded Euclidian division of the polynomial a by a base α to compute t ( · ) A ; extracting Boolean shares a 1 ⋅ B from n low bits of t by performing an arithmetic share to Boolean share (A2B) conversion on t (·) A and performing an AND with ζ - 1, where ζ = -α -1 is a power of 2; unmasking a 1 by combining Boolean shares of a 1 ⋅ B ; calculating arithmetic shares a 0 ⋅ A of the low part a 0 ; and performing a cryptographic function using a 1 and a 0 ⋅ A .
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公开(公告)号：EP4390438A1
公开(公告)日：2024-06-26
申请号：EP23215219.9
申请日：2023-12-08
申请人： NXP B.V.
CPC分类号： G01S5/0289 , G01S5/06 , G01S19/015 , H04W64/00 , G01S5/0205
摘要： In an ultra-wideband (UWB) communication network, a controller anchor changes which anchor of a group of anchors serves as initiator for each of multiple ranging rounds. Based on the capabilities of the anchors in the UWB communication network, the controller selects among multiple modes for designating which anchor serves as initiator for each ranging round. In a first mode, the anchors take turns serving as the initiator for successive ranging rounds in round robin fashion. In a second mode, the anchors randomly take turns serving as the initiator for ranging rounds. By dynamically selecting an initiator for each ranging round, launching a successful jamming attack becomes significantly more complicated.
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公开(公告)号：EP4354788A1
公开(公告)日：2024-04-17
申请号：EP23201452.2
申请日：2023-10-03
申请人： NXP B.V.
CPC分类号： H04L9/004 , H04L9/3093 , H04L9/3247 , H04L2209/1220130101 , H04L2209/2620130101
摘要： Various embodiments relate to a fault detection system and method for a digital signature algorithm, including: producing a digital signature of a message using a digital signature algorithm; storing parameters from a last round of the digital signature algorithm; executing the last round of the digital signature algorithm using the stored parameters to produce a check signature; comparing the digital signature to the check signature; and outputting the digital signature when the digital signature is the same as the check signature.
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公开(公告)号：EP4351082A1
公开(公告)日：2024-04-10
申请号：EP23201307.8
申请日：2023-10-02
申请人： NXP B.V.
摘要： Various embodiments relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including matrix multiplication for lattice-based cryptography in a processor, the instructions, including: applying a first function to the rows of a matrix of polynomials to generate first outputs, wherein the first function excludes the identity function; adding an additional row to the matrix of polynomials to produce a modified matrix, wherein each element in the additional row is generated by a second function applied to a column of outputs associated with each element in the additional row; multiplying the modified matrix with a vector of polynomials to produce an output vector of polynomials; applying a verification function to the output vector that produces an indication of whether a fault occurred in the multiplication of the modified matrix with the vector of polynomials; and carrying out a cryptographic operation using output vector when the verification function indicates that no fault occurred in the multiplication of the modified matrix with the vector of polynomials.
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公开(公告)号：EP4418606A1
公开(公告)日：2024-08-21
申请号：EP24157024.1
申请日：2024-02-12
申请人： NXP B.V.
发明人： Schoenauer, Markus , Azouaoui, Melissa , Bronchain, Olivier , Schneider, Tobias , van Vredendaal, Christine
CPC分类号： H04L9/3247 , H04L9/3093
摘要： A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a fault detection in a digital signature algorithm in a processor, the instructions, including: computing vector z based on a secret nonce vector y, a first secret key vector s1, and a challenge polynomial c, wherein vectors z, y, and s1 include l polynomials having n coefficients, wherein polynomial c has n coefficients, and wherein l and n are integers; computing a difference value between all of the coefficients of the polynomials in the vector z; computing a number of how many of the computed difference values are outside a specified value range; computing a digital signature for an input message; and rejecting the digital signature when the computed number is greater than a threshold value.
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公开(公告)号：EP4395227A1
公开(公告)日：2024-07-03
申请号：EP23218505.8
申请日：2023-12-20
申请人： NXP B.V.
CPC分类号： H04L9/003 , H04L9/3093 , H04L2209/0820130101 , H04L2209/04620130101 , H04L9/085
摘要： A device may include a computer-readable memory and an integrated circuit including a processor configured to implement a cryptographic operation, wherein the cryptographic operation enables computation of a cryptographic result using a bit masking value y. The processor may be configured to access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y, for each bit index in the set of bit indexes, calculate an adaptive share value in which the bit value associated with the bit index is masked, and execute a cryptographic operation using the adaptive share value.
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公开(公告)号：EP4344122A1
公开(公告)日：2024-03-27
申请号：EP23198828.8
申请日：2023-09-21
申请人： NXP B.V.
发明人： Azouaoui, Melissa , Kuzovkova, Yulia , Schneider, Tobias , Schoenauer, Markus , van Vredendaal, Christine
摘要： Various embodiments relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using masked compressing of coefficients of a polynomial having n s arithmetic shares for lattice-based cryptography in a processor, the instructions, including: shifting a first arithmetic share of the n s arithmetic shares by an input mask λ 1 ; scaling the shifted first arithmetic share by a value based on a first compression factor δ and a masking scaling factor ϕ 1 ; shifting the scaled first arithmetic share by a value based on the masking scaling factor ϕ 1 ; scaling a second to n s shares of the n s arithmetic shares by a value based on the first compression factor δ and the masking scaling factor ϕ 1 ; converting the n s scaled arithmetic shares to n s Boolean shares; right shifting the n s Boolean shares based upon the masking scaling factor ϕ 1 and a second compression factor ϕ 2 ; XORing an output mask λ 2 with the shifted first Boolean share to produce n s compressed Boolean shares; and carrying out a cryptographic operation using the n s arithmetic shares when the n s compressed Boolean shares indicates that the coefficients of the polynomial are within boundary values.
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