公开(公告)号：EP4386754A1

公开(公告)日：2024-06-19

申请号：EP23211133.6

申请日：2023-11-21

Applicant: NXP B.V.

Inventor： Chakravarty, Suhas ,  Welker, James Andrew

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40618 ,  G11C11/40622 ,  G11C11/40611 ,  G06F13/1636 ,  G11C11/40603 ,  G11C2211/406220130101

Abstract: A refresh circuit selects a candidate bank for refreshing from various banks of a dynamic random access memory (DRAM). Initially, the refresh circuit checks if any bank is idle (e.g., is not targeted for memory operations). If two or more banks are idle, the candidate bank is selected based on a count of accesses targeted to each occupied bank and bank-pair distances between each pair of idle and occupied banks. Conversely, if all banks are occupied, the refresh circuit selects the candidate bank based on a count of data accesses targeted to each bank and/or a count of parity accesses targeted to each bank. Each data access has the same type as that scheduled for execution on the DRAM. Once the candidate bank is selected, the refresh circuit triggers the refresh of the candidate bank.

公开(公告)号：EP4361826A1

公开(公告)日：2024-05-01

申请号：EP23204357.0

申请日：2023-10-18

Applicant: NXP B.V.

Inventor： Welker, James Andrew ,  Kumar, Vaibhav ,  Kaul, Rohit Kumar ,  Sethi, Ankush

IPC: G06F13/16 ,  G06F9/50

CPC classification number: G06F13/1663 ,  G06F9/5016 ,  G06F13/161

Abstract: Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

公开(公告)号：EP4361869A1

公开(公告)日：2024-05-01

申请号：EP23205324.9

申请日：2023-10-23

Applicant: NXP B.V.

Inventor： Sethi, Ankush ,  Kaul, Rohit Kumar ,  Welker, James Andrew ,  Kumar, Vaibhav ,  Refaeli, Jehoda

IPC: G06F21/62

CPC classification number: G06F21/6218 ,  G06F21/71

Abstract: An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

公开(公告)号：EP4083842A1

公开(公告)日：2022-11-02

申请号：EP22166707.4

申请日：2022-04-05

Applicant: NXP B.V.

Inventor： Tkacik, Thomas E. ,  Waters, Geoffrey Paul ,  Mongia, Mohit ,  Welker, James Andrew ,  Coric, Srdjan

IPC: G06F21/79 ,  G06F12/14 ,  G06F21/72

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.