公开(公告)号：EP4369413A1

公开(公告)日：2024-05-15

申请号：EP23207667.9

申请日：2023-11-03

申请人： NXP B.V.

发明人： Boter, Johan Dick ,  Dubois, Jerome Guillaume Anna ,  van Duuren, Michiel Jos

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/788

摘要： A multi-time programmable memory cell is provided. The multi-time programmable memory cell includes a floating gate formed on a field oxide region formed on a semiconductor substrate. A control gate is formed on the field oxide region and located parallel to a first portion of the floating gate. A program-erase electrode is formed on the field oxide region and proximate to a second portion of the floating gate. A first well region and a second well region are formed in the semiconductor substrate such that a channel region is formed between the first well region and the second well region with a third portion of the floating gate overlaying the channel region.

公开(公告)号：EP2779173B1

公开(公告)日：2018-08-15

申请号：EP14157024.2

申请日：2014-02-27

申请人： NXP B.V.

发明人： van Duuren, Michiel Jos ,  Storms, Maurits Mario Nicolaas ,  van Bussel, Erik Maria

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C7/18 ,  G11C16/24 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/24

摘要： A flash memory array includes memory sectors of two transistors (2T) AND memory cells (S(1,1,1), A(1,1,1) transistors). Within each of the memory sectors (104-1, 104-2), a row of sector selection transistors (SSTL1, SSTL2) is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line (BL1, BL2, BL3), independent from the row of sector selection transistors.

公开(公告)号：EP2779173A3

公开(公告)日：2014-12-10

申请号：EP14157024.2

申请日：2014-02-27

申请人： NXP B.V.

发明人： van Duuren, Michiel Jos ,  Storms, Maurits Mario Nicolaas ,  van Bussel, Erik Maria

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C7/18 ,  G11C16/24

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/24

摘要： A flash memory array includes memory sectors of two transistors (2T) AND memory cells (S(1,1,1), A(1,1,1) transistors). Within each of the memory sectors (104-1, 104-2), a row of sector selection transistors (SSTL1, SSTL2) is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line (BL1, BL2, BL3), independent from the row of sector selection transistors.

公开(公告)号：EP2779173A2

公开(公告)日：2014-09-17

申请号：EP14157024.2

申请日：2014-02-27

申请人： NXP B.V.

发明人： van Duuren, Michiel Jos ,  Storms, Maurits Mario Nicolaas ,  van Bussel, Erik Maria

IPC分类号： G11C11/56 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/24

摘要： A flash memory array includes memory sectors of two transistors (2T) AND memory cells (S(1,1,1), A(1,1,1) transistors). Within each of the memory sectors (104-1, 104-2), a row of sector selection transistors (SSTL1, SSTL2) is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line (BL1, BL2, BL3), independent from the row of sector selection transistors.

摘要翻译： 闪存阵列包括两个晶体管（2T）和存储单元（S（1,1,1），A（1,1,1）晶体管）的存储扇区。 在每个存储器扇区（104-1,104-2）内，配置一行扇区选择晶体管（SSTL1，SSTL2），使得通过向位施加电压来控制将数据写入存储器扇区内的存储器列 线（BL1，BL2，BL3），与行选择晶体管无关。