Clock recovery method and clock recovery arrangement for coherent polarisation multiplex receivers
    1.
    发明公开
    Clock recovery method and clock recovery arrangement for coherent polarisation multiplex receivers 有权
    极地化的复合机器人技术与自动化技术

    公开(公告)号:EP2375603A1

    公开(公告)日:2011-10-12

    申请号:EP10001212.9

    申请日:2010-02-05

    IPC分类号: H04J14/06

    摘要: Component signal values (XI, XQ; YI, YQ) are derived from component signals (xi, xq, yi, yq) and fed to least one fixed equaliser (EQU) which generates equalizer output signals (X IE , X QE , Y IE , Y QE ) . These signals are fed to phase error detectors (PD3, PD4) generating phase error signals (X PE3 Y PE4 ). These phase error signals (X PEi ) are combined with further phase error signals (X PE1 , Y PE2 ) derived by further error detectors (PD1, PD2) receiving signal values from further equalizers and/or the component signal values (XI, XO ; YI, YQ) directly from sample units (15, 16).

    摘要翻译: 分量信号值(XI,XQ; YI,YQ)从分量信号(xi,xq,yi,yq)导出,并馈送给产生均衡器输出信号的最小一个固定均衡器(EQU)(X IE,X QE,Y IE ,Y QE)。 这些信号被馈送到产生相位误差信号(X PE3Y PE4)的相位误差检测器(PD3,PD4)。 这些相位误差信号(X PEi)与进一步的误差检测器(PD1,PD2)导出的进一步的相位误差信号(XPE1,YPE2)组合,从另外的均衡器和/或分量信号值(XI,XO; YI,YQ)直接从样本单位(15,16)。