公开(公告)号：EP2492902A4

公开(公告)日：2014-04-02

申请号：EP09848579

申请日：2009-11-19

Applicant: PANASONIC CORP

Inventor： MATSUI MASAFUMI ,  ONO SHINYA

IPC: G09G3/32 ,  G09G3/20 ,  H01L51/50

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0876 ,  G09G2310/0251

Abstract: A display panel device includes: an organic EL element (13); a capacitor (14) including first and second capacitor electrodes; a driving transistor (11) having a gate connected to the first capacitor electrode for allowing a drain current to flow through the organic EL element (13) and a source connected to the second capacitor electrode; a selecting transistor (12) switchably interconnecting a data line (20) and the first capacitor electrode for supplying a signal voltage to the capacitor (14); a switching transistor (16) switchably interconnecting the drain of the driving transistor (11) and a positive power line (24); and a controller. The controller is configured to: turn ON the selecting transistor (12) while the switching transistor (16) is ON to supply the signal voltage to the capacitor and flow a current between the source of the driving transistor (11) and the second capacitor electrode; and, after predetermined time period, turn OFF the switching transistor (16) to cause non-conduction between the positive power line (24) and the drain of the driving transistor (11).

公开(公告)号：EP2500895A4

公开(公告)日：2014-04-16

申请号：EP09848578

申请日：2009-11-19

Applicant: PANASONIC CORP

Inventor： MATSUI MASAFUMI ,  ONO SHINYA

IPC: G09G3/30 ,  G09G3/20 ,  H01L51/50

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0876 ,  G09G2310/0262 ,  G09G2320/0223

Abstract: A display panel device includes: an organic EL element (13); a capacitor (14); a driving transistor (11) that passes a drain current through the organic EL element (13); a data line (20) that supplies a signal voltage to the capacitor (14); a selecting transistor (12) that switchably interconnects the data line (20) and the capacitor (14); and a controller. The controller is configured to: apply a predetermined bias voltage to a second capacitor electrode to prevent a flow of the drain current; turn ON the selecting transistor (12) to supply the signal voltage to a first capacitor electrode; apply a reverse bias voltage to the second capacitor electrode to flow a discharge current between a source of the driving transistor (11) and the second capacitor electrode; and turn OFF the selecting transistor (12), after a lapse of a predetermined period of time since the discharge current is caused to flow, to stop the supply of the signal voltage to the first capacitor electrode.

公开(公告)号：EP2362371A4

公开(公告)日：2013-03-06

申请号：EP09848580

申请日：2009-11-19

Applicant: PANASONIC CORP

Inventor： MATSUI MASAFUMI ,  ONO SHINYA

IPC: G09G3/30 ,  G09G3/20 ,  H01L51/50

CPC classification number: G09G3/3233 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/0251 ,  G09G2320/0223

公开(公告)号：EP2838200A4

公开(公告)日：2015-04-29

申请号：EP12806326

申请日：2012-04-10

Applicant: PANASONIC CORP

Inventor： TSUGE HITOSHI ,  MATSUI MASAFUMI

IPC: H03K19/0175 ,  G11C19/28

CPC classification number: H03K3/00 ,  G11C19/184 ,  G11C19/28

Abstract: A buffer circuit driving method for driving a buffer circuit including: an output terminal (26); a first transistor (21) connected to a signal source (23) of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal (26); and a second transistor (22) connected to a voltage source (27) that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal (26), includes: causing the first transistor (21) to switch to a conducting state in a period (C) where the clock signal is of the first voltage; and causing the first transistor (21) and the second transistor (22) to switch to the conducting state in a period where the clock signal is of the second voltage, following the period (C) where the clock signal is of the first voltage.

公开(公告)号：EP2429263A4

公开(公告)日：2013-09-04

申请号：EP10761422

申请日：2010-04-06

Applicant: PANASONIC CORP

Inventor： OKUMOTO KENJI ,  MATSUI MASAFUMI ,  OHTA TAKASHI ,  KORESAWA KOUHEI

IPC: H05B33/12 ,  H01L27/32 ,  H01L51/52 ,  H05B33/02 ,  H05B33/22

CPC classification number: H01L27/322 ,  H01L27/3211 ,  H01L51/5284

Abstract: An organic EL display device (1) including organic EL light-emitting regions which includes a red-light emitting layer (111), a green-light emitting layer (112), and a blue-light emitting layer (113) that are arranged on a main substrate (101) includes: a first light-adjusting layer (109) including a first portion (B) and a second portion (M), the first portion selectively transmitting desired blue light, and the second portion absorbing visible light other than at least the desired blue light; and a second light-adjusting layer (106) selectively absorbing light with a wavelength between desired red light and desired green light at an entire surface, in which the blue light-emitting layer (113) is overlaid with the first portion (B), and a bank which is a non-light emitting portion is overlaid with the second portion (M). The first portion and the second portion may be integrally formed of a same material, and the second portion may absorb an entire range of visible light.

公开(公告)号：EP2485567A4

公开(公告)日：2012-08-29

申请号：EP09851232

申请日：2009-11-10

Applicant: PANASONIC CORP

Inventor： KORESAWA KOUHEI ,  MATSUI MASAFUMI ,  OKUMOTO KENJI

IPC: H05B33/12 ,  G02B5/20 ,  H01L51/50 ,  H05B33/02

CPC classification number: G02B5/201 ,  H01L27/3211 ,  H01L27/322