摘要:
A variable bi-phase modulator circuit for microwave signals comprises a quadrature power divider (1) having signal input and output ports (2 and 3) and two control ports (4 and 5), and comprises two variable resistors each having an input port (11). In accordance with the invention each of the two variable resistors comprises first and second microwave field-effect transistors (F1 and F2) the drains of which are coupled together via an intermediate resistor (R). These resistors can be formed using microwave monolithic integrated circuit technology and can have very good impedance characteristics. The input port (11) of the variable resistor comprises a connection to the intermediate resistor (R) and to the drain of the first transistor (F2). Each transistor is connected with zero dc bias between its source and drain and has a channel resistance which changes with change in gate voltage (VG1, VG2). A shunt stub (L1, L2) is connected to the drain of each transistor (F1, F2) to at least partially compensate at the frequency of operation of the transistor for the source to drain capacitance and for shifts in reference plane due to changes in the gate voltage of each transistor.
摘要:
A variable bi-phase modulator circuit for microwave signals comprises a quadrature power divider (1) having signal input and output ports (2 and 3) and two control ports (4 and 5), and comprises two variable resistors each having an input port (11). In accordance with the invention each of the two variable resistors comprises first and second microwave field-effect transistors (F1 and F2) the drains of which are coupled together via an intermediate resistor (R). These resistors can be formed using microwave monolithic integrated circuit technology and can have very good impedance characteristics. The input port (11) of the variable resistor comprises a connection to the intermediate resistor (R) and to the drain of the first transistor (F2). Each transistor is connected with zero dc bias between its source and drain and has a channel resistance which changes with change in gate voltage (VG1, VG2). A shunt stub (L1, L2) is connected to the drain of each transistor (F1, F2) to at least partially compensate at the frequency of operation of the transistor for the source to drain capacitance and for shifts in reference plane due to changes in the gate voltage of each transistor.