公开(公告)号：EP2355351A1

公开(公告)日：2011-08-10

申请号：EP10305092.8

申请日：2010-01-27

申请人： Primachip

发明人： Dufaza, Christian ,  Ihs, Hassan

IPC分类号： H03K5/13 ,  H03M1/00

CPC分类号： H03K5/133

摘要： An improved pulse generator for driving return-to-zero (RTZ) circuitry sensitive to noise coupling and clock jitter is described. It is characterized it comprises means for generating a pulse from a system clock (250), a delay line (210) driven by the system clock (250), decoding means associated to the delay line for shifting away (280, 282) the active level of the pulse from transitions of the system clock(250), and in that it is arranged so that the delay line is locked on the system clock (250) and the active level (285) of the pulse is determined by the delay line.

摘要翻译： 描述了一种用于驱动对噪声耦合和时钟抖动敏感的归零（RTZ）电路的改进的脉冲发生器。 其特征在于它包括用于从系统时钟（250）产生脉冲的装置，由系统时钟（250）驱动的延迟线（210），与延迟线相关联的解码装置，用于移动（280,282）活动 由系统时钟（250）的转变引起的脉冲电平，并且其被布置为使得延迟线被锁定在系统时钟（250）上，并且脉冲的有效电平（285）由延迟线 。