公开(公告)号：EP0854509A1

公开(公告)日：1998-07-22

申请号：EP98100462.5

申请日：1998-01-13

申请人： Programmable Microelectronics Corporation

发明人： Chang, Shang-De Ted, Progr. Microelectronics Corp. ,  Ly, Binh, Programmable Microelectronics Corp.

IPC分类号： H01L21/8239

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

摘要翻译： 一种半导体制造工艺允许高电压晶体管，逻辑晶体管和存储单元的制造，其中，根据需要用于子0.3微米设备的几何形状，所述逻辑晶体管的栅极氧化比非的隧道氧化物厚度薄 易失性存储器细胞，而不在存储器单元的隧道氧化物的逻辑晶体管或污染的栅极氧化物的不希望的污染。 在一个，实施例的存储器单元的隧道氧化物生长到厚度希望的。 在下一步骤中的，而这些用作存储单元（多个）的浮栅掺杂的多晶硅层被立即沉积在存储器单元的隧道氧化物，由此保护隧道氧化物从污染在随后的掩模和蚀刻步骤。 则逻辑晶体管和高电压晶体管的栅氧化物的栅氧化层生长到厚度希望的。