公开(公告)号：EP2073395A2

公开(公告)日：2009-06-24

申请号：EP08165585.4

申请日：2001-11-20

申请人： QUALCOMM Incorporated

发明人： Easton, Kenneth D. ,  Black, Peter, J. c/o QUALCOMM Incorporated

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04B1/709 ,  H04B2001/70935

摘要： A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

摘要翻译： 接收器单元包括以特定采样率接收和存储数字化样本的第一缓冲器，以及从第一缓冲器检索数字化样本的段并且使用特定参数值集处理检索到的段的数据处理器。 数据处理器基于具有比采样率高的（例如，或多次）的频率的处理时钟来操作。 可以通过从第一缓冲器检索和处理数字化样本的多个部分来处理接收信号的多个实例。 接收器单元通常还包括接收和处理发射信号以提供数字化样本的接收机以及为数据处理器调度任务的控制器。 数据处理器可以被设计为包括相关器，符号解调和组合器，第一累加器和第二缓冲器，或其组合。 相关器将所取回的数字化样本片段用相应的PN解扩序列片段解扩，以提供相关样本，由符号解调和组合器进一步处理以提供处理后的符号。 第二缓冲器存储经处理的符号，并且可以被设计为提供经处理符号的去交织。

公开(公告)号：EP2285008A3

公开(公告)日：2013-03-13

申请号：EP10182473.8

申请日：2001-11-20

申请人： Qualcomm Incorporated

发明人： Easton, Kenneth D. ,  Black, Peter J.

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04B1/709 ,  H04B2001/70935

摘要： A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

公开(公告)号：EP2073395A3

公开(公告)日：2011-05-11

申请号：EP08165585.4

申请日：2001-11-20

申请人： QUALCOMM Incorporated

发明人： Easton, Kenneth D. ,  Black, Peter, J. c/o QUALCOMM Incorporated

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04B1/709 ,  H04B2001/70935

摘要： A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

公开(公告)号：EP2285008A2

公开(公告)日：2011-02-16

申请号：EP10182473.8

申请日：2001-11-20

申请人： Qualcomm Incorporated

发明人： Easton, Kenneth D. ,  Black, Peter J.

IPC分类号： H04B1/707

CPC分类号： H04B1/707 ,  H04B1/709 ,  H04B2001/70935

摘要： A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer, the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

摘要翻译： 接收器单元包括以特定采样率接收和存储数字化样本的第一缓冲器，以及从第一缓冲器检索数字化样本的段并且使用特定参数值集处理检索到的段的数据处理器。 数据处理器基于具有比采样率高的（例如，或多次）的频率的处理时钟来操作。 接收信号的多个实例可以通过从第一缓冲器检索和处理数字化采样的多个段来处理，接收机单元通常还包括接收和处理发射信号以提供数字化采样的接收机，以及控制器，其为 数据处理器。 数据处理器可以被设计为包括相关器，符号解调和组合器，第一累加器和第二缓冲器，或其组合。 相关器将所取回的数字化样本片段用相应的PN解扩序列片段解扩，以提供相关样本，由符号解调和组合器进一步处理以提供处理后的符号。 第二缓冲器存储经处理的符号，并且可以被设计为提供经处理符号的去交织。