公开(公告)号：EP1332552A2

公开(公告)日：2003-08-06

申请号：EP01992057.8

申请日：2001-11-03

申请人： QUALCOMM INCORPORATED

发明人： MOHSENI, Jafar, M. ,  BUTLER, Brian, K. ,  JOHN, Deepu ,  ZHANG, Haitao

IPC分类号： H03H1/00

CPC分类号： H03H17/0657 ,  H03H17/0226 ,  H03H17/0238 ,  H03H17/06 ,  H03H17/0607

摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

公开(公告)号：EP1332552B1

公开(公告)日：2009-01-14

申请号：EP01992057.8

申请日：2001-11-03

申请人： QUALCOMM INCORPORATED

发明人： MOHSENI, Jafar, M. ,  BUTLER, Brian, K. ,  JOHN, Deepu ,  ZHANG, Haitao

IPC分类号： H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0657 ,  H03H17/0226 ,  H03H17/0238 ,  H03H17/06 ,  H03H17/0607

摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

公开(公告)号：EP1066559B1

公开(公告)日：2005-06-08

申请号：EP99911150.3

申请日：1999-03-04

申请人： QUALCOMM INCORPORATED

发明人： SIH, Gilbert, C. ,  ZOU, Quizhen ,  JHA, Sanjay, K. ,  KANG, Inyup ,  LIN, Jian ,  MOTIWALA, Quaeed ,  JOHN, Deepu ,  ZHANG, Li ,  ZHANG, Haitao ,  LEE, Way-Shing ,  SAKAMAKI, Charles, E. ,  KANTAK, Prashant, A.

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

公开(公告)号：EP1245102A1

公开(公告)日：2002-10-02

申请号：EP00982277.6

申请日：2000-11-29

申请人： QUALCOMM INCORPORATED

发明人： MOHSENI, Mohammad, Jafar ,  BUTLER, Brian ,  JOHN, Deepu ,  ZHANG, Haitao

IPC分类号： H04L27/18

CPC分类号： H04L27/206 ,  H04L27/2082

摘要： In applications employing phase-shift keying modulation, a phase rotator (200, 202) as disclosed herein is used to rotate the constellation of signal vectors before carrier modulation in order to maximize modulator output power. Such a rotator (200, 202) may be applied in the digital domain (to complex signals having either binary-valued or multi-valued components) or in the analog domain.

公开(公告)号：EP1388214A2

公开(公告)日：2004-02-11

申请号：EP01986123.6

申请日：2001-11-03

申请人： QUALCOMM INCORPORATED

发明人： BUTLER, Brian, K. ,  MOHSENI, Jafar, M. ,  JOHN, Deepu ,  ZHANG, Haitao

IPC分类号： H04B1/707

CPC分类号： H04B1/7093 ,  H04B1/707

摘要： A spreading system according to an embodiment of the invention spreads two data signals. The system produces a filtered signal that is based on one of the data signals and an output signal that is based on both of the data signals. In one example, a spreading system is used to perform QPSK spreading of two data signals, including separate processing of the two data signals, in a practical manner. Such separate control may include filtering and/or gain control.

公开(公告)号：EP1066559A1

公开(公告)日：2001-01-10

申请号：EP99911150.3

申请日：1999-03-04

申请人： QUALCOMM Incorporated

发明人： SIH, Gilbert, C. ,  ZOU, Quizhen ,  JHA, Sanjay, K. ,  KANG, Inyup ,  LIN, Jian ,  MOTIWALA, Quaeed ,  JOHN, Deepu ,  ZHANG, Li ,  ZHANG, Haitao ,  LEE, Way-Shing ,  SAKAMAKI, Charles, E. ,  KANTAK, Prashant, A.

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0886 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3885 ,  G06F9/3893 ,  G06F15/7807

摘要： A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).