公开(公告)号：EP1974255B1

公开(公告)日：2018-08-22

申请号：EP07710244.0

申请日：2007-01-22

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F12/1027

摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

公开(公告)号：EP1974255A1

公开(公告)日：2008-10-01

申请号：EP07710244.0

申请日：2007-01-22

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F12/1027

摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

公开(公告)号：EP2118753B1

公开(公告)日：2013-07-10

申请号：EP08729314.8

申请日：2008-02-07

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/04 ,  G06F12/10

CPC分类号： G06F12/04 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.

公开(公告)号：EP2118753A1

公开(公告)日：2009-11-18

申请号：EP08729314.8

申请日：2008-02-07

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/04

CPC分类号： G06F12/04 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.

公开(公告)号：EP1899820A2

公开(公告)日：2008-03-19

申请号：EP06785811.8

申请日：2006-06-27

申请人： QUALCOMM INCORPORATED

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/10

CPC分类号： G06F9/3802 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

摘要： A processor includes a memory configured to store data in a plurality of pages, a TLB, and a TLB controller. The TLB is configured to search, when accessed by an instruction having a virtual address, for address translation information that allows the virtual address to be translated into a physical address of one of the plurality of pages, and to provide the address translation information if the address translation information is found within the TLB. The TLB controller is configured to determine whether a current instruction and a subsequent instruction seek access to a same page within the plurality of pages, and if so, to prevent TLB access by the subsequent instruction, and to utilize the results of the TLB access of a previous instruction for the current instruction.