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    PROGRAMMING HARDWARE REGISTERS USING A PIPELINED REGISTER BUS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES
    2.
    发明公开
    PROGRAMMING HARDWARE REGISTERS USING A PIPELINED REGISTER BUS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES 审中-公开
    使用流水线寄存器总线编程硬件寄存器及相关方法，系统和设备

    公开(公告)号：EP3234787A1

    公开(公告)日：2017-10-25

    申请号：EP15797533.5

    申请日：2015-11-06

    申请人： Qualcomm Incorporated

    发明人： CHANG, Chi-Wen ,  HSIAO, Yi-Pin ,  MANDAVA, Praveen ,  WU, Vickie; Youmin ,  ZERWICK, Adam; Andrew

    IPC分类号： G06F13/42

    CPC分类号： G06F13/404 ,  G06F13/364 ,  G06F13/4022 ,  G06F13/4256 ,  G06F13/4282

    摘要： Programming hardware registers using a pipelined register bus, and related methods, systems, and apparatuses are disclosed. In one aspect, a method for communicating over a register bus comprises initiating, at a register bus master, a request comprising an address, and passing the request from the register bus master to a first register bus slave of a processor module via a register bus. The method further comprises decoding the address at a module core of the processor module, and determining whether the address corresponds to the processor module. The method also comprises, responsive to determining that the address corresponds to the processor module, processing the request by the module core, and passing the same request as-is to a second register bus slave. The method additionally comprises, responsive to determining that the address does not correspond to the processor module, passing the same request as-is to the second register bus slave.

    摘要翻译： 使用流水线寄存器总线编程硬件寄存器以及相关方法，系统和装置被公开。 在一个方面，一种用于通过寄存器总线进行通信的方法包括：在寄存器总线主设备处启动包括地址的请求，并且经由寄存器总线将来自寄存器总线主设备的请求传递到处理器模块的第一寄存器总线从设备 。 该方法还包括在处理器模块的模块核心解码地址，并且确定地址是否对应于处理器模块。 该方法还包括，响应于确定地址对应于处理器模块，由模块核心处理该请求，并且将相同的请求原样传递到第二寄存器总线从设备。 该方法还包括，响应于确定地址不对应于处理器模块，将相同的请求原样传递到第二寄存器总线从设备。