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    MIXED-WIDTH SIMD OPERATIONS HAVING EVEN-ELEMENT AND ODD-ELEMENT OPERATIONS USING REGISTER PAIR FOR WIDE DATA ELEMENTS
    2.
    发明公开
    MIXED-WIDTH SIMD OPERATIONS HAVING EVEN-ELEMENT AND ODD-ELEMENT OPERATIONS USING REGISTER PAIR FOR WIDE DATA ELEMENTS 审中-公开

    公开(公告)号：EP3326060A1

    公开(公告)日：2018-05-30

    申请号：EP16732213.0

    申请日：2016-06-21

    申请人： Qualcomm Incorporated

    发明人： MAHURIN, Eric Wayne ,  INGLE, Ajay Anant

    IPC分类号： G06F9/30

    摘要： Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

    SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS
    4.
    发明公开
    SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS 审中-公开

    公开(公告)号：EP3335127A1

    公开(公告)日：2018-06-20

    申请号：EP16742129.6

    申请日：2016-07-11

    申请人： Qualcomm Incorporated

    发明人： MAHURIN, Eric Wayne

    IPC分类号： G06F17/16 ,  G06F9/00

    CPC分类号： G06F9/3001 ,  G06F7/00 ,  G06F7/5443 ,  G06F9/30036 ,  G06F17/16

    摘要： Systems and methods relate to multiply-and-horizontal-reduce operations, implemented in a digital filter, for example. A single instruction multiple data (SIMD) instruction comprising a first vector comprising M+C multiplicand elements, wherein M and C are positive integers and a second vector comprising M+C corresponding multiplier elements, wherein the C multiplier elements have a value of 1, is received. Using M multipliers in a processor, M multiplications of M multiplicand elements with corresponding M multiplier elements which do not include the C multiplier elements whose values are 1, are performed to generate M products. The C multiplicand elements whose corresponding C multiplier elements have values of 1 are added to or vertically accumulated with the M products.

    CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS
    7.
    发明公开
    CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS 审中-公开

    公开(公告)号：EP3353623A1

    公开(公告)日：2018-08-01

    申请号：EP16767464.7

    申请日：2016-09-08

    申请人： Qualcomm Incorporated

    发明人： MAHURIN, Eric Wayne ,  PATIL, Sanjay Bhagawan ,  SAINT-LAURENT, Martin Pierre

    IPC分类号： G06F1/32

    CPC分类号： G06F1/26 ,  G06F1/3206 ,  G06F1/329 ,  Y02D10/24

    摘要： Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.

    TABLE LOOKUP USING SIMD INSTRUCTIONS
    9.
    发明公开
    TABLE LOOKUP USING SIMD INSTRUCTIONS 审中-公开

    公开(公告)号：EP3335108A1

    公开(公告)日：2018-06-20

    申请号：EP16742126.2

    申请日：2016-07-11

    申请人： Qualcomm Incorporated

    发明人： MAHURIN, Eric Wayne ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  HOYLE, David ,  ZENG, Mao ,  GAN, Kim-Chyan

    IPC分类号： G06F9/30

    摘要： Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.