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1.发明公开Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward 审中-公开维特比幸存存储器架构，低延迟和进程注册交换，追踪和追查转发
公开(公告)号：EP2362549A2
公开(公告)日：2011-08-31
申请号：EP10154940.0
申请日：2010-02-26
发明人： Kosakowski, Martin
IPC分类号： H03M13/41
CPC分类号： H03M13/4192 , H03M13/413 , H03M13/4169 , H03M13/4176
摘要： In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.
摘要翻译： 在各个方面，本发明描述的系统和卷积编码信号的解码表示的方法，例如，电信信号：诸如命令或在数字电信中使用的信号的内容。 在各种实施例中检查本发明的方面提供的系统和提高效率，速度和功率搜索过程的消耗的方法通过提供架构和方法用于并行处理的编码的数据记录各个部分，使用多个和任选特殊设计， 专用存储器寄存器和多路复用器。
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2.发明公开
公开(公告)号：EP2562952A1
公开(公告)日：2013-02-27
申请号：EP11178722.2
申请日：2011-08-24
CPC分类号： H04L1/0026 , H04L1/06
摘要： A method for estimating channel state information (CSI) for a communication channel is disclosed. Theoretical channel capacities are calculated using combinations of rank indicator (RI) and precoding matrix index (PMI) values. A number of these theoretical channel capacities are selected and used for determining an optimum combination of channel quality indicator (CQI) values, RI values and PMI values. This combination of values is subsequently transmitted as CSI. 1.
摘要翻译： 公开了一种用于估计通信信道的信道状态信息（CSI）的方法。 使用秩指示符（RI）和预编码矩阵索引（PMI）值的组合来计算理论信道容量。 选择这些理论信道容量的数量并用于确定信道质量指示符（CQI）值，RI值和PMI值的最佳组合。 值的这种组合随后作为CSI发送。 1。
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公开(公告)号：EP2413551A1
公开(公告)日：2012-02-01
申请号：EP10171305.5
申请日：2010-07-29
发明人： Weng, Jianfeng , Velez, Edgar Filberto , Panicker, John Puthen , Kosakowski, Martin , Duggan, Jason Robert
IPC分类号： H04L25/02
CPC分类号： H04L25/0206 , H04L5/0048 , H04L25/0232 , H04L27/2647
摘要： A method for channel estimation includes receiving data at a number of frequency intervals in a frequency band over a number of first time intervals. A first set of channel estimates is determined (152) for each pilot symbol (106) within the data over a second time interval comprising at least one first time interval, and time-direction interpolation (154) is performed to determine a second set of channel estimates for a number of data portions in a frequency interval using the first set of channel estimates. The frequency interval comprises a data portion comprising a pilot symbol (106). Frequency-direction interpolation (156) is performed to determine a third set of channel estimates for each first time interval. The time-direction interpolation (154) and the frequency-direction interpolation (156) can be performed in reverse order with the channel estimates generated by the frequency-direction interpolation (156) being used as inputs for time-direction interpolation (154).
摘要翻译： 用于信道估计的方法包括以多个第一时间间隔在频带中以多个频率间隔接收数据。 在包括至少一个第一时间间隔的第二时间间隔内，针对数据内的每个导频符号（106）确定第一组信道估计（152），并且执行时间方向内插（154）以确定第二组 使用第一组信道估计在频率间隔中的多个数据部分的信道估计。 频率间隔包括包括导频符号（106）的数据部分。 频率方向内插（156）被执行以确定每个第一时间间隔的第三组信道估计。 时间方向内插（154）和频道内插（156）可以以频率方向内插（156）生成的信道估计用作时间插值输入（154）的相反顺序执行。
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4.发明公开Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward 审中-公开维特比幸存存储器架构，低延迟和进程注册交换，追踪和追查转发
公开(公告)号：EP2362549A3
公开(公告)日：2011-10-26
申请号：EP10154940.0
申请日：2010-02-26
发明人： Kosakowski, Martin
IPC分类号： H03M13/41
CPC分类号： H03M13/4192 , H03M13/413 , H03M13/4169 , H03M13/4176
摘要： In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.
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