Distribution of error correction and compression processing
    1.
    发明公开
    Distribution of error correction and compression processing 失效
    Verteilung von Fehlerkorrektur und Kompressionverarbeitung

    公开(公告)号:EP1014644A2

    公开(公告)日:2000-06-28

    申请号:EP99125410.3

    申请日:1993-05-14

    IPC分类号: H04L29/06

    摘要: A method and apparatus for distributing the data error correction and compression processing load between a modem (DCE) and a host data terminal equipment (DTE) enables modem implementation with minimal cost, power dissipation, and size. The DTE has a CPU and an associated memory. The memory contains a data transmission program for execution by the CPU to produce output data for transmitting, and at least a data compression algorithm and a data error checking algorithm for execution by the CPU under control of the data transmission program to asynchronously deliver data according to the data transmission program to a modem for synchronous transmission. The modem included in the DCE asynchronously received the data from the DTE and synchronously transmits it as output data. Due to the distribution of the data processing algorithms into the memory of the DTE, the DCE can be operated simultaneously in communication and control modes. Moreover, the modem can be controlled during data transmission or reception in response to a 〈DLE〉 code in combination with a predetermined control code.

    摘要翻译: 用于在调制解调器(DCE)和主机数据终端设备(DTE)之间分配数据纠错和压缩处理负载的方法和装置以最小的成本,功耗和尺寸实现调制解调器的实现。 DTE具有CPU和相关的内存。 存储器包含用于由CPU执行以产生用于发送的输出数据的数据传输程序,以及用于在数据传输程序的控制下由CPU执行的数据压缩算法和数据错误检查算法,以根据数据传输程序异步传送数据 数据传输程序到调制解调器进行同步传输。 包含在DCE中的调制解调器异步地从DTE接收数据,同步地将其作为输出数据发送。 由于数据处理算法分配到DTE的存储器中,DCE可以在通信和控制模式下同时工作。 此外,可以在数据发送或接收期间响应于与预定的控制代码组合的&lang&DLE&rang&code来控制调制解调器。

    Distribution of modem error correction and compression processing
    2.
    发明公开
    Distribution of modem error correction and compression processing 失效
    在einem Modem和Kompressionsrechnung的Verteilung der Fehlerkorrektur。

    公开(公告)号:EP0572843A1

    公开(公告)日:1993-12-08

    申请号:EP93107903.2

    申请日:1993-05-14

    IPC分类号: H04L29/06

    摘要: A method and apparatus for distributing the data error correction and compression processing load between a modem (DCE) and a host data terminal equipment (DTE) enables modem implementation with minimal cost, power dissipation, and size. The DTE has a CPU and an associated memory. The memory contains a data transmission program for execution by the CPU to produce output data for transmitting, and at least a data compression algorithm and a data error checking algorithm for execution by the CPU under control of the data transmission program to asynchronously deliver data according to the data transmission program to a modem for synchronous transmission. The modem included in the DCE asynchronously received the data from the DTE and synchronously transmits it as output data. Due to the distribution of the data processing algorithms into the memory of the DTE, the DCE can be operated simultaneously in communication and control modes. Moreover, the modem can be controlled during data transmission or reception in response to a 〈DLE〉 code in combination with a predetermined control code.

    摘要翻译: 用于在调制解调器(DCE)和主机数据终端设备(DTE)之间分配数据纠错和压缩处理负载的方法和装置以最小的成本,功耗和尺寸实现调制解调器的实现。 DTE具有CPU和相关的内存。 存储器包含用于由CPU执行以产生用于发送的输出数据的数据传输程序,以及用于在数据传输程序的控制下由CPU执行的数据压缩算法和数据错误检查算法,以根据数据传输程序异步传送数据 数据传输程序到调制解调器进行同步传输。 包含在DCE中的调制解调器异步地从DTE接收数据,同步地将其作为输出数据发送。 由于数据处理算法分配到DTE的存储器中,DCE可以在通信和控制模式下同时工作。 此外,可以在数据发送或接收期间响应于&Lang&DLE&Rang&code与预定控制码的组合来调制调制解调器。

    Distribution of error correction and compression processing
    3.
    发明公开
    Distribution of error correction and compression processing 失效
    Verteilung von Fehlerkorrektur und Kompressionverarbeitung

    公开(公告)号:EP1014644A3

    公开(公告)日:2005-07-13

    申请号:EP99125410.3

    申请日:1993-05-14

    IPC分类号: H04L29/06

    摘要: A method and apparatus for distributing the data error correction and compression processing load between a modem (DCE) and a host data terminal equipment (DTE) enables modem implementation with minimal cost, power dissipation, and size. The DTE has a CPU and an associated memory. The memory contains a data transmission program for execution by the CPU to produce output data for transmitting, and at least a data compression algorithm and a data error checking algorithm for execution by the CPU under control of the data transmission program to asynchronously deliver data according to the data transmission program to a modem for synchronous transmission. The modem included in the DCE asynchronously received the data from the DTE and synchronously transmits it as output data. Due to the distribution of the data processing algorithms into the memory of the DTE, the DCE can be operated simultaneously in communication and control modes. Moreover, the modem can be controlled during data transmission or reception in response to a 〈DLE〉 code in combination with a predetermined control code.

    摘要翻译: 用于在调制解调器(DCE)和主机数据终端设备(DTE)之间分配数据纠错和压缩处理负载的方法和装置以最小的成本,功耗和尺寸实现调制解调器的实现。 DTE具有CPU和相关的内存。 存储器包含用于由CPU执行以产生用于发送的输出数据的数据传输程序,以及用于在数据传输程序的控制下由CPU执行的数据压缩算法和数据错误检查算法,以根据数据传输程序异步传送数据 数据传输程序到调制解调器进行同步传输。 包含在DCE中的调制解调器异步地从DTE接收数据,同步地将其作为输出数据发送。 由于数据处理算法分配到DTE的存储器中,DCE可以在通信和控制模式下同时工作。 此外,可以在数据发送或接收期间响应于&Lang&DLE&Rang&code与预定控制码的组合来调制调制解调器。