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1.发明授权RÜCKGEKOPPELTES SCHIEBEREGISTER ZUM ERZEUGEN VON PSEUDOZUFALLSZAHLENFOLGEN DARSTELLENDEN DIGITALEN SIGNALEN 失效反馈移位寄存器产生伪RAND FOLLOW数字信号SHOWING
公开(公告)号：EP0681760B1
公开(公告)日：1997-03-26
申请号：EP94904989.4
申请日：1994-01-26
CPC分类号： G06F7/584 , G06F2207/581 , G06F2207/583 , H03K3/84
摘要： A feedback shift register for generating digital signals representing series of pseudo-random numbers has n-aries and exclusive OR-circuits in the feedback logic, as well as a clock generator. In order to generate digital signals with a feedback shift register suitable for subsequent digital processing, the clock generator (17) is connected to the n-aries (11, 12, 13, 14, 15) of the shift register (10) by a controllable gate circuit (18) which blocks one clock pulse per 2n clock pulses (CLK) of the clock generator (17).
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2.发明公开RÜCKGEKOPPELTES SCHIEBEREGISTER ZUM ERZEUGEN VON PSEUDOZUFALLSZAHLENFOLGEN DARSTELLENDEN DIGITALEN SIGNALEN 失效FOR产生伪RAND反馈移位寄存器FOLLOW代表的数字信号。
公开(公告)号：EP0681760A1
公开(公告)日：1995-11-15
申请号：EP94904989.0
申请日：1994-01-26
CPC分类号： G06F7/584 , G06F2207/581 , G06F2207/583 , H03K3/84
摘要： A feedback shift register for generating digital signals representing series of pseudo-random numbers has n-aries and exclusive OR-circuits in the feedback logic, as well as a clock generator. In order to generate digital signals with a feedback shift register suitable for subsequent digital processing, the clock generator (17) is connected to the n-aries (11, 12, 13, 14, 15) of the shift register (10) by a controllable gate circuit (18) which blocks one clock pulse per 2n clock pulses (CLK) of the clock generator (17).
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