公开(公告)号：EP1111791A1

公开(公告)日：2001-06-27

申请号：EP00403396.5

申请日：2000-12-04

申请人： SONY CORPORATION

发明人： Kouji, Hirairi

IPC分类号： H03K19/21 ,  G06F7/50

CPC分类号： G06F7/501 ,  H03K19/215

摘要： A logic circuit capable of suppressing occurrence of wraparound of signals. capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit (12) for receiving a first logic signal A and a second logic signal B taking a logic "1" or "0" and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit (11) for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B. and an interpolation circuit (13) for compulsorily setting the output level of the dual signal at the level of the logic "1" when the output level of the exclusive-OR is the logic "0", while compulsorily setting the output level of the exclusive-OR at the level of the logic "0" when the output level of the dual signal is the logic "1",

摘要翻译： 一种能够抑制信号环绕的发生的逻辑电路。 能够降低功耗，另外实现电路规模的缩小和工作速度的提高以及使用其的全加器，其中提供了异或产生电路（12），用于接收第一逻辑 信号A和逻辑“1”或“0”并产生第一逻辑信号A和第二逻辑信号B的异或的第二逻辑信号B，用于接收第一逻辑信号的双信号产生电路 信号A和第二逻辑信号B，并产生第一逻辑信号A和第二逻辑信号B的异或的双信号;以及插值电路（13），用于强制地将双信号的输出电平设置在 当异或的输出电平为逻辑“0”时逻辑“1”的电平，同时在双向输出的输出电平时强制将异或的输出电平设置在逻辑“0”的电平 信号是逻辑“1”，