公开(公告)号：EP2885874A1

公开(公告)日：2015-06-24

申请号：EP13750869.3

申请日：2013-08-14

Applicant: ST-Ericsson SA

Inventor： HOUDEBINE, Marc ,  RIEUBON, Sébastien ,  KIEFFER, Julien

IPC: H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0891 ,  H03L7/0895 ,  H03L7/093

Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of α * I and the second current has a magnitude of β *I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (α-β) * I.

公开(公告)号：EP2499741A1

公开(公告)日：2012-09-19

申请号：EP10781483.2

申请日：2010-11-12

Applicant: ST-Ericsson SA

Inventor： RIEUBON, Sébastien

IPC: H03K5/159

CPC classification number: H03K5/159

Abstract: The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items.

公开(公告)号：EP2499741B1

公开(公告)日：2016-08-31

申请号：EP10781483.2

申请日：2010-11-12

Applicant: ST-Ericsson SA

Inventor： RIEUBON, Sébastien

IPC: H03K5/159

CPC classification number: H03K5/159