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公开(公告)号：EP2204997A2
公开(公告)日：2010-07-07
申请号：EP09179044.4
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
摘要： A system for processing packet streams, the system comprising: a system data-bus for transferring packets of data; a system memory connected to the data-bus for storing packets; a first processor connected to the data-bus, arranged to retrieve secure packets from the system memory via the data-bus; and a second processor connected to the data-bus, programmed to perform security processing by applying one or more security algorithms to the secure packets to generate at least partially security-processed packets. The first processor is programmed so as to control the security processing of a previously retrieved packet by the second processor, the security processing involving a delay whilst the first processor awaits the return of a security-processed packet from the second processor; and the first processor is arranged to further process a previously security-processed packet to generate a corresponding output data during the delay.
摘要翻译： 一种用于处理分组流的系统，所述系统包括：用于传送数据分组的系统数据总线; 连接到数据总线以存储分组的系统存储器; 连接到数据总线的第一处理器，被布置成经由数据总线从系统存储器检索安全数据包; 以及连接到所述数据总线的第二处理器，被编程为通过将一个或多个安全算法应用于所述安全分组来执行安全处理，以生成至少部分安全处理的分组。 第一处理器被编程以便由第二处理器控制先前检索的分组的安全处理，所述安全处理涉及延迟，而第一处理器等待来自第二处理器的安全处理分组的返回; 并且第一处理器被布置为在延迟期间进一步处理先前经过安全处理的分组以产生相应的输出数据。
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公开(公告)号：EP2204996A3
公开(公告)日：2012-05-02
申请号：EP09179042.8
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24 , H04N21/4385
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
摘要： A system comprising: a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets. The system further comprises first queuing circuitry, separate from the data-bus and memory, to queue packets for transfer from the first to the second processor; and second packet queuing circuitry, separate from the data-bus and memory, to queue packets for transfer from the second to the first processor. The first processor transfers the secure packets to the second processor via the first queuing circuitry for security processing. The second processor returns the security-processed packets to the first processor via the second queuing circuitry. The first processor then further processes the security-processed packets, other than by applying a security algorithm, to generate output data for a user output apparatus.
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公开(公告)号：EP2204997A3
公开(公告)日：2012-01-25
申请号：EP09179044.4
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
摘要： A system for processing packet streams, the system comprising: a system data-bus for transferring packets of data; a system memory connected to the data-bus for storing packets; a first processor connected to the data-bus, arranged to retrieve secure packets from the system memory via the data-bus; and a second processor connected to the data-bus, programmed to perform security processing by applying one or more security algorithms to the secure packets to generate at least partially security-processed packets. The first processor is programmed so as to control the security processing of a previously retrieved packet by the second processor, the security processing involving a delay whilst the first processor awaits the return of a security-processed packet from the second processor; and the first processor is arranged to further process a previously security-processed packet to generate a corresponding output data during the delay.
摘要翻译： 一种用于处理分组流的系统，该系统包括：用于传送数据分组的系统数据总线; 连接到数据总线的系统存储器，用于存储分组; 连接到数据总线的第一处理器，其被设置为经由数据总线从系统存储器取回安全分组; 以及连接到数据总线的第二处理器，被编程为通过将一个或多个安全算法应用于安全分组来执行安全处理，以产生至少部分安全处理的分组。 第一处理器被编程以控制第二处理器对先前检索到的分组的安全处理，当第一处理器等待来自第二处理器的安全处理分组的返回时，安全处理涉及延迟; 并且第一处理器被布置为在延迟期间进一步处理先前安全处理的分组以生成对应的输出数据。
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公开(公告)号：EP2204997B1
公开(公告)日：2013-05-22
申请号：EP09179044.4
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
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公开(公告)号：EP2204996B1
公开(公告)日：2013-05-22
申请号：EP09179042.8
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24 , H04N21/4385
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
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公开(公告)号：EP2204996A2
公开(公告)日：2010-07-07
申请号：EP09179042.8
申请日：2009-12-14
发明人： Bolton, Martin , Pearson, Paul , Emslie, Diarmuid
IPC分类号： H04N7/24
CPC分类号： H04N21/4385 , H04N21/2389 , H04N21/434 , H04N21/43853
摘要： A system comprising: a data-bus, system memory, a first processor arranged to receive an input stream, and a second processor programmed to apply one or more security algorithms to secure packets of the input stream to generate at least partially security-processed packets. The system further comprises first queuing circuitry, separate from the data-bus and memory, to queue packets for transfer from the first to the second processor; and second packet queuing circuitry, separate from the data-bus and memory, to queue packets for transfer from the second to the first processor. The first processor transfers the secure packets to the second processor via the first queuing circuitry for security processing. The second processor returns the security-processed packets to the first processor via the second queuing circuitry. The first processor then further processes the security-processed packets, other than by applying a security algorithm, to generate output data for a user output apparatus.
摘要翻译： 一种系统，包括：数据总线，系统存储器，布置成接收输入流的第一处理器，以及被编程为应用一个或多个安全算法来保护输入流的分组以产生至少部分安全处理分组的第二处理器 。 该系统还包括与数据总线和存储器分离的第一排队电路，以排队从第一处理器传送到第二处理器; 以及与数据总线和存储器分离的第二分组排队电路，以将分组从第二处理器传送到第一处理器。 第一处理器经由第一排队电路将安全数据包传送到第二处理器，用于安全处理。 第二处理器经由第二排队电路将经安全处理的分组返回给第一处理器。 然后，除了通过应用安全算法之外，第一处理器进一步处理安全处理的分组，以生成用户输出设备的输出数据。
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