公开(公告)号：EP0752800A2

公开(公告)日：1997-01-08

申请号：EP96110753.9

申请日：1996-07-03

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Yeung, Louise

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5619

摘要： A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.

摘要翻译： 一种用于将从第一存储元件传送到第二存储元件的数据进行字节打包的可扩展打包电路。 打包电路包括字包装电路，其接收第一位宽的数据包并将其存储为与第二存储元件的位宽相当的第二位宽的数据包。 同时，字包装电路消除了包含在来自第一存储元件的数据包中的无效字。 打包电路还包括字节打包电路，其在将数据传送到第二存储元件以进行连续存储之前，去除第二位宽的数据包中的无效字节。

公开(公告)号：EP0772371B1

公开(公告)日：2004-01-02

申请号：EP96307882.9

申请日：1996-10-31

申请人： Sun Microsystems, Inc.

发明人： Oskouy, Rasoul M. ,  Palaniraj, Sunderraj V. ,  Gaytan, Andre J.

IPC分类号： H04Q11/04 ,  H04L12/26

CPC分类号： H04L43/50 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04Q11/0478

公开(公告)号：EP0752800B1

公开(公告)日：2004-01-02

申请号：EP96110753.9

申请日：1996-07-03

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Yeung, Louise

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5619

公开(公告)号：EP0752800A3

公开(公告)日：1999-09-22

申请号：EP96110753.9

申请日：1996-07-03

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Yeung, Louise

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5619

摘要： A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.

公开(公告)号：EP0752801A3

公开(公告)日：2000-01-19

申请号：EP96110754.7

申请日：1996-07-03

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Oskouy, Rasoul M.

IPC分类号： H04Q11/04 ,  H04L12/56

CPC分类号： H04Q11/0478 ,  H04L29/06 ,  H04L49/90 ,  H04L69/324 ,  H04L2012/5616 ,  H04L2012/5652

摘要： A method and network interface for controlling the flow of data between a and an ATM network is provided. The network interface resides on an ATM interface and includes a state machine for each channel supported by the ATM interface. The state machine moves from state to state based on the contents of a local buffer, indications that data for the channel is ready to be transferred from the host computer to the local buffer, and the status of operations that transfer data for the channel from the host computer to the local buffer. The ATM interface includes a DMA unit and a segmentation unit that operate responsive to the states of the various state machines to avoid inefficient transfer operations. Specifically, the DMA unit does not attempt to move data for a channel from the host computer to the local buffer if the state of the state machine for the channel indicates that (1) there is no more data in the host computer for the channel or (2) there is no more room in the local buffer to receive data for the channel from the host computer. The segmentation unit does not attempt to transmit cells for a channel when the state of the state machine for the channel indicates that the local buffer does not contain enough data for the channel to construct a cell for the channel.

公开(公告)号：EP0752796A3

公开(公告)日：1999-05-26

申请号：EP96110414.8

申请日：1996-06-27

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Oskouy, Rasoul M.

IPC分类号： H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A transmission data buffer and method for buffering data to be transmitted from a host computer to an asynchronous transfer mode (ATM) telecommunications network. The transmission data buffer comprises a plurality if FIFO memories, one for each channel which is established on the connection to the ATM network. A load engine loads packets of data (e.g. AAL5, AAL5-MPEG, TCP packets) into particular FIFO memories in the transmission buffer according to a load schedule queue. The data is removed from the FIFO memories by an unload engine according to entries in a bandwidth group table. The unload engine segments the data as it is removed from the FIFOs, by removing one ATM cell payload (48-bytes) at a time, and adds the ATM cell header data. The unload engine can also generate AAL5 packet CRC fields and add a control and length field to the cell data segmented from an AAL5 packet. The transmission buffer memory includes at least one tag bit for each data word which is set to indicate the beginning and end of packets in the FIFO memories.

公开(公告)号：EP0752802A3

公开(公告)日：1999-05-19

申请号：EP96110991.5

申请日：1996-07-08

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Gentry, Denton E., Jr. ,  Oskouy, Rasoul M.

IPC分类号： H04Q11/04

CPC分类号： H04N21/2381 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04N21/64307 ,  H04Q11/0478

摘要： A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ("TX") DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common said overhead information for the block of data to avoid the TX DMA engine reaccessing the data descriptor to obtain the same overhead information for each frame being transferred.

公开(公告)号：EP0772371A1

公开(公告)日：1997-05-07

申请号：EP96307882.9

申请日：1996-10-31

申请人： SUN MICROSYSTEMS, INC.

发明人： Oskouy, Rasoul M. ,  Palaniraj, Sunderraj V. ,  Gaytan, Andre J.

IPC分类号： H04Q11/04 ,  H04L12/26

CPC分类号： H04L43/50 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04Q11/0478

摘要： A method and an apparatus for verifying a network transporter under test which is able to perform the test and produce test results by posting test packets through network transporter without requiring large amounts of memory and producing results in a short period of time. The present invention utilizes one or more FIFO (First In First Out) buffers in which plurality of components of each packet is stored just as each packet is posted to the network transporter under test. As soon as the corresponding packet is received on the other side of the network transporter, plurality of components and the receive packet are compared and a test result is produced. As soon as such comparison is performed and completed and the test results are produced, the corresponding plurality of components stored in the FIFO is discarded and the corresponding memory space used is freed up for the next packet's test information.

公开(公告)号：EP0752802B1

公开(公告)日：2003-09-24

申请号：EP96110991.5

申请日：1996-07-08

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Gentry, Denton E., Jr. ,  Oskouy, Rasoul M.

IPC分类号： H04Q11/04

CPC分类号： H04N21/2381 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04N21/64307 ,  H04Q11/0478

公开(公告)号：EP0752802A2

公开(公告)日：1997-01-08

申请号：EP96110991.5

申请日：1996-07-08

申请人： SUN MICROSYSTEMS, INC.

发明人： Gaytan, Andre J. ,  Gentry, Denton E., Jr. ,  Oskouy, Rasoul M.

IPC分类号： H04Q11/04

CPC分类号： H04N21/2381 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04N21/64307 ,  H04Q11/0478

摘要： A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ("TX") DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common said overhead information for the block of data to avoid the TX DMA engine reaccessing the data descriptor to obtain the same overhead information for each frame being transferred.

摘要翻译： 一种用于优化从存储元件传送具有有限尺寸的多个帧的数据块的效率的电路和方法。 该电路包括发送（“TX”）DMA引擎和TX分段引擎。 TX DMA引擎负责从专用于该特定TX数据缓冲器的数据描述符访问TX数据缓冲器内的数据块的开销信息。 TX DMA引擎还负责从本地存储的存储器元件读取数据块。 TX分段引擎负责将数据块分割成与多个帧相对应的多个信元分组。 每个单元包共同地包含用于数据块的所述开销信息，以避免TX DMA引擎重新访问数据描述符，以便为每个被传送的帧获得相同的开销信息。