公开(公告)号：EP4216282A1

公开(公告)日：2023-07-26

申请号：EP22199501.2

申请日：2022-10-04

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Seungku ,  PARK, Yonghee ,  SHIN, Dong-Gwan ,  KIM, Dae Sin ,  KIM, Sangyong ,  YOU, Joohyung

IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04

摘要： A semiconductor device includes a substrate (100) including an active pattern (AP1), a channel pattern (CH1) on the active pattern and including semiconductor patterns (SP1, SP2, SP3) vertically stacked and spaced apart from each other, a source/drain pattern (SD1) connected to the semiconductor patterns, a gate electrode (GE) on the semiconductor patterns and extending in a first direction (D2), and a gate insulating layer (GI) between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction (D2), and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region (PA1) on one of the opposite side surfaces of the first semiconductor pattern and a second region (PA2) on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region (TK1) may be greater than a thickness of the second region (TK2).

公开(公告)号：EP4002438A1

公开(公告)日：2022-05-25

申请号：EP21188419.2

申请日：2021-07-29

申请人： Samsung Electronics Co., Ltd.

发明人： CHO, Keun Hwi ,  KWON, Sangdeok ,  KIM, Dae Sin ,  KIM, Dongwon ,  PARK, Yonghee ,  CHO, Hagju

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092

摘要： A semiconductor device includes first and second active patterns (AP1, AP2) respectively on the first and second active regions (PR1, NR1) of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact (GC) electrically connected to the gate electrode, a first metal layer (M1) on the active and gate contacts and including a first and second power line (VDD, VSS), and first and second gate cutting patterns (CT) below the first and second power lines. The first active pattern includes a first channel pattern between a pair of first source/drain patterns. The second active pattern includes a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns cover the outermost side surfaces of the first and second channel patterns, respectively.