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公开(公告)号：EP4391388A9
公开(公告)日：2024-08-07
申请号：EP22879792.4
申请日：2022-03-21
发明人： CHEN, Xiao
IPC分类号： H03M1/10
CPC分类号： H03M1/10 , H03M1/12 , H03M1/164 , H03M1/1215
摘要： Provided in the present application are an analog-to-digital converter and an inter-stage gain calibration method. The analog-to-digital converter comprises a sampling and holding circuit, which is configured to periodically sample and hold an analog input signal; a first-stage analog-to-digital sub-converter, which is configured to convert the analog input signal into a first digital signal, convert the first digital signal into a first voltage signal, and process a difference between the analog input signal and the first voltage signal, so as to obtain a second voltage signal; a first processing circuit, which is configured to perform clock synchronization and period delay on the first digital signal, so as to obtain a second digital signal; an inter-stage amplifier, which is realized by using an open-loop structure, and is configured to amplify the second voltage signal to obtain a third voltage signal; a second-stage analog-to-digital sub-converter, which is configured to convert the third voltage signal into a third digital signal; a second processing circuit, which is configured to perform clock synchronization on the third digital signal, so as to obtain a fourth digital signal; and an adder, which is configured to combine and add the second digital signal as a high-bit codeword and the fourth digital signal as a low-bit codeword, so as to obtain a digital output signal.
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公开(公告)号：EP4391388A1
公开(公告)日：2024-06-26
申请号：EP22879792.4
申请日：2022-03-21
发明人： CHEN, Xiao
IPC分类号： H03M1/10
摘要： Provided in the present application are an analog-to-digital converter and an inter-stage gain calibration method. The analog-to-digital converter comprises a sampling and holding circuit, which is configured to periodically sample and hold an analog input signal; a first-stage analog-to-digital sub-converter, which is configured to convert the analog input signal into a first digital signal, convert the first digital signal into a first voltage signal, and process a difference between the analog input signal and the first voltage signal, so as to obtain a second voltage signal; a first processing circuit, which is configured to perform clock synchronization and period delay on the first digital signal, so as to obtain a second digital signal; an inter-stage amplifier, which is realized by using an open-loop structure, and is configured to amplify the second voltage signal to obtain a third voltage signal; a second-stage analog-to-digital sub-converter, which is configured to convert the third voltage signal into a third digital signal; a second processing circuit, which is configured to perform clock synchronization on the third digital signal, so as to obtain a fourth digital signal; and an adder, which is configured to combine and add the second digital signal as a high-bit codeword and the fourth digital signal as a low-bit codeword, so as to obtain a digital output signal.
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