公开(公告)号：EP1076309A1

公开(公告)日：2001-02-14

申请号：EP00305955.7

申请日：2000-07-13

申请人： Semiconductor Technology Academic Research Center

发明人： Shibata, Tadashi ,  Konda, Masahiro, Itsutsubashi Dormitory ,  Ohmi, Tadahiro

IPC分类号： G06G7/14

CPC分类号： G06G7/14

摘要： Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.

摘要翻译： 公开了一种可以用简单电路实现的半导体计算电路，能够高速执行模拟计算，以计算表示第一信号电压和第二信号电压之差的绝对值电压。 半导体计算电路包括：第一MOS晶体管，具有浮动栅极和电容耦合到浮动栅极的控制栅极; 具有浮置栅极和与栅极电容耦合的控制栅极的第二MOS晶体管，其源极连接到第一MOS晶体管的源极; 写入电路，其中施加到第一和第二MOS晶体管的控制栅极的规定电压将第一MOS晶体管的浮置栅极处的电位设置为等于第一信号电压的值，并且还将电位设置在 第二MOS晶体管的浮置栅极等于通过从规定电压减去第一信号电压而获得的值; 以及差分电压计算电路，用于计算表示通过从规定电压减去第二信号电压而获得的值的电压，并且其中：在通过写入电路设置第一和第二MOS晶体管之后，当差分电压计算的输出电压 电路施加到第一MOS晶体管的控制栅极，同时将第二信号电压施加到第二MOS晶体管的控制栅极，绝对值电压表示第一信号电压和第二信号电压之间的差 被输出。

公开(公告)号：EP1076310A1

公开(公告)日：2001-02-14

申请号：EP00305956.5

申请日：2000-07-13

申请人： Semiconductor Technology Academic Research Center

发明人： Shibata, Tadashi ,  Konda, Masahiro ,  Ohmi, Tadahiro

IPC分类号： G06G7/14

CPC分类号： G11C11/5621 ,  G06G7/14 ,  G11C27/005 ,  H04N19/94

摘要： Disclosed are a computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences, and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference comprises a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 comprises a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences comprises a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

摘要翻译： 公开了一种能够计算与高速模拟计算的绝对差异的计算电路，能够计算绝对差的和的计算装置以及适用于这种计算电路或装置的简单电路可实现的半导体计算电路 。 能够计算绝对差的计算电路包括大输入选择电路1，其输出第一信号或第二信号（较大者），小输入选择电路2，输出第一和第二信号，无论信号较小者，以及 减法电路3，其从大输入选择电路1的输出中减去小输入选择电路2的输出。减法电路3包括电容器6，设置在电容器6的第一端和第一开关4之间的第一开关4， 大输入选择电路1的输出，设置在电容器6的第一端和小输入选择电路2的输出之间的第二开关5，以及设置在电容器6的第二端子与端子之间的第三开关7 连接到规定的电位。 能够计算绝对差的和的计算装置包括多个这样的计算电路，并且通过使用求和电路来计算计算电路的输出之和。