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    Time-division multiple-access communication system
    2.
    发明公开
    Time-division multiple-access communication system 失效
    Mehrfachzugriff mit Zeitverschachtelung Kommunikationsanordnung

    公开(公告)号：EP0878924A2

    公开(公告)日：1998-11-18

    申请号：EP98108467.6

    申请日：1998-05-08

    申请人： Sharp Kabushiki Kaisha ,  Hitachi, Ltd. ,  MITSUBISHI DENKI KABUSHIKI KAISHA ,  Communications Research Laboratory, Ministry of Posts and Telecommunications ,  Nippon Telegraph and Telephone Corporation ,  NTT MOBILE COMMUNICATIONS NETWORK INC. ,  YRP Mobile Telecommunications Key Technology Research Laboratories Co., Ltd.

    发明人： Onodera, Tetsuo ,  Usami, Hiroshi ,  Shibuya, Akihiro ,  Moriyama, Eimatus ,  Hamaguchi, Kiyoshi ,  Saito, Yoichi ,  Matsumoto, Tadashi ,  Mizuno, Mitsuhiko

    IPC分类号： H04B7/26

    CPC分类号： H04B7/212

    摘要： The present invention is directed to a TDMA communication system which is adapted to different communication environments or prepares different communication environments and allows each mobile station to be set for working in any one of the different communication environments. This enables the mobile terminal to conduct communications in different communication environments and at different transmission rates. An office communication environment, a walking-speed mobile-communication environment, a vehicle-running-speed mobile-communication environment and a satellite communication environment are separately constructed and connected to each other by a communication network. Each environment system has a mobile exchanging function, a base-station function with a transmitter-receiver and mobile-station function with a transmitter-receiver to realize communication therein. The communication system commonly uses a TDMA format that has a fixed frame-length and a constant number of bits for each of the slots composing the frame. The communication environments have prepared respective sets of communication conditions, each set including a transmission power, a modulating method, the number of multiplexed signals, error-correction, an antenna gain, a frequency hopping value and a diversity value. At each mobile station and each base station, one of plural sets of communication conditions for respective environments is selected to establish communication with each other under the selected environment.

    摘要翻译： 本发明涉及一种TDMA通信系统，其适于不同的通信环境或准备不同的通信环境，并且允许每个移动站被设置用于在不同通信环境中的任何一个中工作。 这使得移动终端能够在不同的通信环境中以不同的传输速率进行通信。 办公通信环境，步行速度移动通信环境，车辆行驶速度移动通信环境和卫星通信环境分别构造并通过通信网络彼此连接。 每个环境系统具有移动交换功能，具有发射机 - 接收机的基站功能和具有发射机 - 接收机的移动台功能，以实现其中的通信。 通信系统通常使用对于构成帧的每个时隙具有固定的帧长度和固定比特数的TDMA格式。 通信环境已经准备了各种通信条件，每组包括传输功率，调制方法，复用信号的数量，纠错，天线增益，跳频值和分集值。 在每个移动站和每个基站处，选择用于各个环境的多组通信条件之一，以在所选择的环境下建立彼此的通信。

    Coded modulation communication system
    5.
    发明公开
    Coded modulation communication system 失效
    KodiertesModulationsübertragungssystem。

    公开(公告)号：EP0348305A2

    公开(公告)日：1989-12-27

    申请号：EP89401793.8

    申请日：1989-06-23

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    发明人： Saito, Yoichi ,  Nakamura, Yasuhisa ,  Aikawa, Satoru ,  Takanashi, Hitoshi

    IPC分类号： H04L27/34 ,  H03M13/12

    CPC分类号： H03M13/25 ,  H04L27/3427

    摘要： In Trellis coded modulation system in which an input digital signal in parallel form is encoded by a convolutional encoder which adds an additional bit to the input digital signal for error correction purpose, and a mapping circuit designates amplitude and phase for each symbol for QAM signal, the number of parallel bits at output of said convolutional encoder is the same as the number of parallel bits of an input digital signal. An input digital signal is first rate converted so that m+n bits in every T period is converted to m bits in every T′ period, where T′=(m/(m+n))·T. The convolutional encoder adds n number of bits so that the total number of parallel bits is m+n, which is applied to the mapping circuit. In a receive side, a receive signal having m+n bits in every T′ period is decoded through an error correction decoder which provides m bits in every T′ period, then, the decoded signal is rate converted to m+n bits in every T period. So, the number of parallel bits does not increase in spite of convolutional encoding, but a transmission rate is a little increased. The coding gain in the present invention is improved since the number of levels of the QAM signal is not increased although the bandwidth of the signal is a little increased because of the higher clock rate.

    摘要翻译： 在网格编码调制系统中，其中并行形式的输入数字信号由卷积编码器编码，该卷积编码器将附加位添加到输入数字信号用于纠错目的，并且映射电路指定用于QAM信号的每个符号的幅度和相位， 所述卷积编码器的输出处的并行比特数与输入数字信号的并行比特数相同。 输入数字信号首先进行速率转换，使得每T个周期内的m + n个比特在每个T min周期内被转换成m比特，其中T min =（m /（m + n））。 卷积编码器增加n个位数，使得并行位的总数为m + n，这被施加到映射电路。 在接收侧，通过在每个T min周期内提供m比特的纠错解码器来解码每T分钟周期中具有m + n比特的接收信号，然后解码信号在每个T min周期内被速率转换为m + n比特 T期。 因此，尽管卷积编码，并行比特数也没有增加，但传输速率有所增加。 尽管由于较高的时钟频率，信号的带宽稍微增加，但是由于QAM信号的电平数量不增加，所以本发明中的编码增益得到改善。

    Word synchronization system
    6.
    发明公开
    Word synchronization system 失效
    字同步系统

    公开(公告)号：EP0328977A2

    公开(公告)日：1989-08-23

    申请号：EP89101981.2

    申请日：1989-02-04

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    发明人： Aikawa, Satoru ,  Saito, Yoichi

    IPC分类号： H04L7/04

    CPC分类号： H04L7/048

    摘要： This invention relates to a word synchronization system which receives signals with error correction codes to calculate a syndrome from an initial phase, changes the initial phase when the calculated syndrome is not zero to calculate it anew, and repeats the operation until the time when the particular syndrome becomes zero for the sequence of M time (or the number of testing stages). This invention system is further provided with a synchro­nization slip detecting circuit to judge such a slip out of the synchronization without the necessity to wait for the repetition of the state for M times to thereby enable prompt phase resetting or synchronization establishment.

    摘要翻译： 本发明涉及一种字同步系统，它接收具有纠错码的信号以从初始阶段计算校正子，当计算出的校正子不为零时改变初始阶段重新计算它，并重复该操作直到特定时间 M时间序列（或测试阶段的数量）变为零。 本发明系统进一步提供有一个同步滑动检测电路，用于在不需要等待M次的状态重复的情况下判断这种滑动脱离同步，从而能够进行及时的相位复位或同步建立。

    Multi-level decision circuit
    7.
    发明公开
    Multi-level decision circuit 失效
    多级决策电路

    公开(公告)号：EP0153708A3

    公开(公告)日：1987-10-14

    申请号：EP85101929

    申请日：1985-02-22

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    发明人： Nakamura, Yasuhisa ,  Saito, Yoichi

    IPC分类号： H04L27/06 ,  H04L25/06

    CPC分类号： H04L27/06 ,  H04L25/066 ,  H04L25/067

    摘要： An input multi-level amplitude sgnal of 2 M levels is supplied via a DC level controller (12) to an AD converter (14) for conversion into an N-bit (N being an integer greater than M) digital signal, and M high-order bits of the digital signal are provided as decided outputs. it is decided by a decision means (29) whether a deviation of the DC level of the multi-level amplitude signal at the input side of the AD converter is in excess of a predetermined value. When the deviation of the DC level is decided less than the predetermined value, the outputs of bits less significant that the Mth bit in the digital signal are integrated for input as a DC level control signal into the DC level controller, correcting the deviation of the DC level. When it is decided by the decision means that the deviation of the DC level is greater than the predetermined value, at least one of the M high-order bit outputs in the output digital signal is integrated for input as a DC level control signal into the DC level controller, correcting the deviations of the DC level.

    Multi-level decision circuit
    9.
    发明公开
    Multi-level decision circuit 失效
    多级决策电路。

    公开(公告)号：EP0153708A2

    公开(公告)日：1985-09-04

    申请号：EP85101929.9

    申请日：1985-02-22

    申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

    发明人： Nakamura, Yasuhisa ,  Saito, Yoichi

    IPC分类号： H04L27/06 ,  H04L25/06

    CPC分类号： H04L27/06 ,  H04L25/066 ,  H04L25/067

    摘要： An input multi-level amplitude sgnal of 2 M levels is supplied via a DC level controller (12) to an AD converter (14) for conversion into an N-bit (N being an integer greater than M) digital signal, and M high-order bits of the digital signal are provided as decided outputs. it is decided by a decision means (29) whether a deviation of the DC level of the multi-level amplitude signal at the input side of the AD converter is in excess of a predetermined value. When the deviation of the DC level is decided less than the predetermined value, the outputs of bits less significant that the Mth bit in the digital signal are integrated for input as a DC level control signal into the DC level controller, correcting the deviation of the DC level. When it is decided by the decision means that the deviation of the DC level is greater than the predetermined value, at least one of the M high-order bit outputs in the output digital signal is integrated for input as a DC level control signal into the DC level controller, correcting the deviations of the DC level.