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    PATH REDUNDANT HARDWARE EFFICIENT COMMUNICATIONS INTERCONNECT SYSTEM
    2.
    发明公开
    PATH REDUNDANT HARDWARE EFFICIENT COMMUNICATIONS INTERCONNECT SYSTEM 有权
    与平衡冗余和程序，以皮带场通信AGENCY

    公开(公告)号：EP2186268A1

    公开(公告)日：2010-05-19

    申请号：EP08827466.7

    申请日：2008-08-08

    申请人： Smith, Robert B.

    发明人： Smith, Robert B.

    IPC分类号： H04L12/50

    CPC分类号： H04L49/1515 ,  H04L49/101 ,  H04L49/552

    摘要： A path redundant, hardware efficient communications interconnect (1) has embodiments that can present true any-to-any interconnect capability for first and second pathways (2) and (3) and can utilize double throw switches (25) with or without single throw switches (24) perhaps in staged collectives of sub arrays (4), (5), (6), (9), and (10). A loop-back communications interconnect (22) can be accomplished by an interleaved sub array (26). A quadrilateral center stage sub array (21) can be combined with asymmetric side stage sub arrays for hardware savings that are tenths of a percent of a traditional interconnect and even present eight fold savings over prior reduced hardware interconnects.