公开(公告)号：EP1730840A1

公开(公告)日：2006-12-13

申请号：EP05718373.3

申请日：2005-03-11

申请人： Soisic

发明人： DESORTIAUX, Vincent

IPC分类号： H03K3/011 ,  H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/013

摘要： The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their floating body is set to a potential by means of an appropriate connection, in order to locally reduce their contribution to the overall phase noise of said circuit. It also provides a reduced phase noise master-slave circuit. This circuit includes floating body SOI type transistors, characterised in that the potential of said floating body of the transistors that (60, 61) contribute to said phase noise is set by means of an appropriate connection (64, 65).