公开(公告)号：EP1022858A3

公开(公告)日：2004-01-02

申请号：EP00300359.7

申请日：2000-01-19

申请人： SONY CORPORATION

发明人： Mimachi, Nobumasa, Sony LSI Design Corporation ,  Hashimoto, Minoru ,  Kimura, Hiromasa

IPC分类号： H03M13/00 ,  G11B20/14 ,  G11B20/10

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1461

摘要： A decoding apparatus and data reproduction apparatus which can perform correction of 1T and 2T which inherently cannot exist as EFM signals, reduce processing of an error correction circuit, and improve the playability. Provision is made of an EFM block containing a correction portion for detecting an edge of an RF signal converted to a binary format by the PLL asymmetry correction circuit for NRZ conversion, using a clock generated in the digital PLL circuit for synchronization, detecting 1T and 2T (T is a channel clock period), which inherently cannot exist as EFM signals in format, generated at the time of synchronization, correcting the detected 1T and 2T signals to 0 or 3T in accordance with predetermined conditions to remove the 1T and 2T from the RF signal, and modulating the RF signal from which the 1T and 2T have been removed by EFM and a demodulation circuit for demodulating by EFM a signal after modulation by EFM.

公开(公告)号：EP1022858B1

公开(公告)日：2011-09-07

申请号：EP00300359.7

申请日：2000-01-19

申请人： Sony Corporation

发明人： Mimachi, Nobumasa, Sony LSI Design Corporation ,  Hashimoto, Minoru ,  Kimura, Hiromasa

IPC分类号： H03M13/00 ,  G11B20/14 ,  G11B20/10

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1461

公开(公告)号：EP1022858A2

公开(公告)日：2000-07-26

申请号：EP00300359.7

申请日：2000-01-19

申请人： SONY CORPORATION

发明人： Mimachi, Nobumasa, Sony LSI Design Corporation ,  Hashimoto, Minoru ,  Kimura, Hiromasa

IPC分类号： H03M13/00 ,  G11B20/14

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1461

摘要： A decoding apparatus and data reproduction apparatus which can perform correction of 1T and 2T which inherently cannot exist as EFM signals, reduce processing of an error correction circuit, and improve the playability. Provision is made of an EFM block containing a correction portion for detecting an edge of an RF signal converted to a binary format by the PLL asymmetry correction circuit for NRZ conversion, using a clock generated in the digital PLL circuit for synchronization, detecting 1T and 2T (T is a channel clock period), which inherently cannot exist as EFM signals in format, generated at the time of synchronization, correcting the detected 1T and 2T signals to 0 or 3T in accordance with predetermined conditions to remove the 1T and 2T from the RF signal, and modulating the RF signal from which the 1T and 2T have been removed by EFM and a demodulation circuit for demodulating by EFM a signal after modulation by EFM.

摘要翻译： 能够执行固有地不能作为EFM信号存在的1T和2T的校正的解码装置和数据再现装置，减少误差校正电路的处理并提高可播放性。 提供一个EFM块，其包含校正部分，用于使用在数字PLL电路中产生的用于同步的时钟来检测用于NRZ转换的PLL不对称校正电路来转换为二进制格式的RF信号的边缘，检测1T和2T （T是通道时钟周期），其固有地不能作为在同步时产生的格式的EFM信号存在，根据预定条件将检测到的1T和2T信号校正为0或3T以从1T和2T中移除1T和2T RF信号，以及通过EFM调制1T和2T被去除的RF信号，以及用EFM调制后的信号用EFM解调的解调电路。