公开(公告)号：EP1387484A1

公开(公告)日：2004-02-04

申请号：EP01926146.0

申请日：2001-05-08

申请人： Sony Corporation ,  Sony International (Europe) GmbH

发明人： ABE, Masayoshi, c/o SONY CORPORATION ,  SASHO, Noboru, c/o SONY CORPORATION ,  KRUPEZEVIC, Dragan, SONY INT.(EUROPE) G.M.B.H. ,  BRANKOVIC, Veselin, SONY INT. (EUROPE)G.M.B.H. ,  RATNI, Mohamed, SONY INT. (EUROPE) G.M.B.H.

IPC分类号： H03D1/22 ,  H04B1/30 ,  H04L27/38

CPC分类号： H03D1/2245 ,  H04B1/30

摘要： A high performance demodulator able to realize a further wide band property, low distortion characteristic, and low power consumption in comparison with a conventional multi-port demodulator and having a small fluctuation in characteristics with respect to fluctuation in temperatures and aging including a first branch circuit 1001 for branching a reception signal to first to third three signals; a second branch circuit 1002 for branching a local signal to first and second two signals; a first phase shifter 1003 for shifting the phase of the first local signal from the second branch circuit 1002 by a shift amount θ1; a second phase shifter 1004 for shifting the phase of the second local signal from the second branch circuit 1002 by a shift amount θ2; a first coupler circuit 1005 for coupling the second reception signal from the first branch circuit 1001 and the local signal shifted in the phase by the shift amount θ1 by the first phase shifter 1003; a second coupler circuit 1006 for coupling the third reception signal from the first branch circuit 1001 and the local signal shifted in the phase by the shift amount θ2 by the second phase shifter 1004; a first power detector 1007 for detecting an amplitude component of the first reception signal by the first branch circuit 1001; a second power detector 1008 for detecting the amplitude component of a vector sum signal by the first coupler circuit 1005; a third power detector 1009 for detecting the amplitude component of a vector sum signal by the second coupler circuit 1006; and a multi-port signal-to-IQ signal conversion circuit 1010 receiving output signals P1, P2, and P3 of the first to third power detectors 1007 to 1009 and converting the result to an In-phase signal I(t) and a quadrature signal Q(t) as demodulated signals.

摘要翻译： 与传统的多端口解调器相比，能够实现进一步宽带特性，低失真特性和低功耗的高性能解调器，并且相对于包括第一分支电路的温度和老化的波动，特性波动小 1001，用于将接收信号分支为第一至第三三个信号; 第二分支电路1002，用于将本地信号分支为第一和第二两个信号; 第一移相器1003，用于将来自第二分支电路1002的第一本地信号的相位移位移位量θ1; 第二移相器1004，用于将来自第二分支电路1002的第二本地信号的相位移位移位量θ2; 第一耦合器电路1005，用于耦合来自第一分支电路1001的第二接收信号和由第一移相器1003移相相位移位量θ1的本地信号; 第二耦合器电路1006，用于耦合来自第一分支电路1001的第三接收信号和由第二移相器1004移相移位量θ2的相位的本地信号; 第一功率检测器1007，用于检测第一分支电路1001的第一接收信号的幅度分量; 第二功率检测器1008，用于检测第一耦合器电路1005的矢量和信号的幅度分量; 第三功率检测器1009，用于检测第二耦合器电路1006的矢量和信号的幅度分量; 以及接收第一至第三功率检测器1007至1009的输出信号P1，P2和P3并将结果转换为同相信号I（t）和正交信号I（t）的多端口信号至IQ信号转换电路1010。 信号Q（t）作为解调信号。