利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.008 秒)

    Dual port buffer
    1.
    发明公开
    Dual port buffer 有权
    双端口缓冲区

    公开(公告)号：EP0905610A1

    公开(公告)日：1999-03-31

    申请号：EP98307887.4

    申请日：1998-09-29

    申请人： Stmicroelectronics, Ltd.

    发明人： Warren, Robert

    IPC分类号： G06F5/06

    CPC分类号： G06F5/10

    摘要： Circuitry is described for transferring information from a first timing environment to a second timing environment. The circuitry comprises a dual port RAM having a first port which is responsive to a first timing signal and a second port which is responsive to a second timing signal, a first control circuit which is responsive to the first timing signal, for controlling storage of data in the dual port RAM through the first port and for generating a control signal indicating that data is stored in the dual port RAM. The circuitry also comprises a synchroniser for synchronising the control signal to the second timing signal, and a second control circuit, which is responsive to the second timing signal and the synchronised control signal and is for controlling retrieval of stored data through the second port of the dual port RAM.

    摘要翻译： 描述了用于将信息从第一定时环境传送到第二定时环境的电路。 该电路包括双端口RAM，该双端口RAM具有响应于第一定时信号的第一端口和响应于第二定时信号的第二端口，响应于第一定时信号的第一控制电路，用于控制数据的存储 在双端口RAM中通过第一端口并且用于产生指示数据存储在双端口RAM中的控制信号。 该电路还包括用于使控制信号与第二定时信号同步的同步器和响应于第二定时信号和同步的控制信号并且用于控制通过第二定时信号的第二端口检索存储的数据的第二控制电路 双端口RAM。