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公开(公告)号：EP2176952A1
公开(公告)日：2010-04-21
申请号：EP08775296.0
申请日：2008-07-23
发明人： VANSELOW, Frank , ARNOLD, Matthias
IPC分类号： H03K3/011 , H03K3/0231 , H03L1/00 , H03L7/02 , H03L7/097
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/00 , H03L7/02
摘要： An electronic device, comprises a digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator is provided for comparing the voltage drop across the variable capacitors with a reference voltage level and for providing a DCO output clock signal. Switching means are adapted to alternately switch the variable capacitors to receive either a current from the programmable current source or to be discharged in response to an output signal of the comparator. A clock divider is coupled to an output of the comparator for dividing the DCO output clock signal by a factor N substantially greater than 1, in order to provide a divided clock signal (X). Further, a frequency monitoring stage is provided for receiving the divided clock signal and is adapted to determine the time difference of successive clock periods of the divided clock signal and to generate a feedback signal in response to the determined time difference in order to adapt the frequency of the DCO output clock signal with the feedback signal.
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公开(公告)号：EP2151052B1
公开(公告)日：2012-08-15
申请号：EP08759545.0
申请日：2008-05-13
发明人： REFELD, Thomas , VANSELOW, Frank
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00208
摘要： The present invention relates to a ring oscillator including a plurality of cascaded inverting delay stages, each delay stage includes a differential pair of input transistors, a variable resistive load coupled to each transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, such that the bias current increases, while the variable resistive load decreases and vice versa.
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公开(公告)号：EP2151052A1
公开(公告)日：2010-02-10
申请号：EP08759545.0
申请日：2008-05-13
发明人： REFELD, Thomas , VANSELOW, Frank
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00208
摘要： The present invention relates to a ring oscillator including a plurality of cascaded inverting delay stages, each delay stage includes a differential pair of input transistors, a variable resistive load coupled to each transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, such that the bias current increases, while the variable resistive load decreases and vice versa.
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公开(公告)号：EP2176952B1
公开(公告)日：2012-06-06
申请号：EP08775296.0
申请日：2008-07-23
发明人： VANSELOW, Frank , ARNOLD, Matthias
IPC分类号： H03K3/011 , H03K3/0231 , H03L1/00 , H03L7/02 , H03L7/097
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/00 , H03L7/02
摘要： An electronic device, comprises a digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator is provided for comparing the voltage drop across the variable capacitors with a reference voltage level and for providing a DCO output clock signal. Switching means are adapted to alternately switch the variable capacitors to receive either a current from the programmable current source or to be discharged in response to an output signal of the comparator. A clock divider is coupled to an output of the comparator for dividing the DCO output clock signal by a factor N substantially greater than 1, in order to provide a divided clock signal (X). Further, a frequency monitoring stage is provided for receiving the divided clock signal and is adapted to determine the time difference of successive clock periods of the divided clock signal and to generate a feedback signal in response to the determined time difference in order to adapt the frequency of the DCO output clock signal with the feedback signal.
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