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1.发明公开
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公开(公告)号：EP4268219A1
公开(公告)日：2023-11-01
申请号：EP21844997.3
申请日：2021-12-22
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6.发明公开
公开(公告)号：EP4243333A1
公开(公告)日：2023-09-13
申请号：EP22305273.9
申请日：2022-03-11
摘要： An electronic device is provided for securing and desynchronizing register transfers as a mitigation strategy to side channel attacks that employ power analysis profiling, whereby leakage information produced as a result of register switching at the bit-level, by way of random delay cell insertions, is decorrelated from actual power consumption. The technical effect of the solution constructively produces overlapping of current power profiles/signatures, maximally spanning across bit value profiles of a register, which when analyzed from a Hamming Weight or Distance model introduces a wider time-spread of resulting current power profiles thereby impeding deep learning of the transistor switching/flipping state behavior, and consequently disrupting efficacy of profile/signature matching/mapping of transistor state changes characteristic of a traditional power analysis side channel attack. Other embodiments are disclosed.
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公开(公告)号：EP4191399A1
公开(公告)日：2023-06-07
申请号：EP21306707.7
申请日：2021-12-03
IPC分类号： G06F7/58
摘要： The present invention relates to a method for generating, by a random number generator of a cryptographic system, an independent bit sequence from a binary candidate random stream, said random generator comprising a source of randomness configured to generate a random noise, an analog to digital converter configured to generate a binary raw random stream by digitizing said random noise, said candidate random stream being obtained from said raw random stream, said method comprising:
- performing a test to check the independency of the bits of the binary candidate random stream, comprising :
• acquiring repeatedly (S1), at least one bit from the candidate random stream until said acquired bits form a test sequence comprising at least N first pairs of successive bits, wherein the value of a first bit of each of said first pairs is 0, and N second pairs of successive bits, wherein the value of a first bit of each of said second pairs is 1, N being a predetermined integer, and
counting in said test sequence a number of pairs of successive bits comprising 0 as both first and second bit, called "n00", and/or a number of pairs of successive bits comprising 0 as first bit and 1 as second bit, called "n01", until n00+n01 = N,
and counting in said test sequence a number of pairs of successive bits comprising 1 as both first and second bit, called "n11", and/or a number of pairs of successive bits comprising 1 as first bit and 0 as second bit, called "n10", until n11+n10 = N,
• verifying (S2) if the difference between "n00" and "n10" and/or the difference between "n01" and "n11" for said test sequence is within a predetermined acceptance range,
- if verification is a success, generating (S3) the independent bit sequence from said candidate random stream.
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