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公开(公告)号：EP0007209B1
公开(公告)日：1983-05-04
申请号：EP79301299.8
申请日：1979-07-05
申请人： THE POST OFFICE
CPC分类号： H04L7/0331 , H03L7/0992 , H04L27/2275
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公开(公告)号：EP0007209A1
公开(公告)日：1980-01-23
申请号：EP79301299.8
申请日：1979-07-05
申请人： THE POST OFFICE
CPC分类号： H04L7/0331 , H03L7/0992 , H04L27/2275
摘要： A circuit for producing an output waveform synchronised with the timing of a given waveform, the circuit comprising:
a multiplicity of digital counting stages (16,17) arranged as a frequency divider to produce a frequency-divided output from an input frequency, the division ratio of the frequency divider being settable to either, or any one, of at feast two values, one of said digital counting stages being a divide-by-two circuit arranged to provide said output waveform.
timing comparison means (5) arranged to make repeated comparisons of the timing of an output of the frequency divider with the timing of a reference waveform, and to produce on each comparison a first signal if the output is leading the reference and a second signal if the output is lagging the reference, said timing comparison means comprising a first D-type bistable circuit (5) and a transition detector circuit (3, 4), the output of the transition detector circuit being connected to the CLOCK input of the bistable circuit, and the D input of the bistable circuit being connected to receive the same input as the said divide-by-two circuit forming part of the frequency divider,
integrator means (10, 11) connected to the output of the timing comparison means to integrate the first signal in one direction and the second signal in the opposite direction, and
division ratio setting means (12) to set the division ratio at a first, higher, value if the integrated value exceeds a threshold in the one direction, and at a second lower value if the irte- grated value exceeds the threshold in the opposite direction.
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