公开(公告)号：EP3940780A1

公开(公告)日：2022-01-19

申请号：EP21185755.2

申请日：2021-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： YANG, Feng-Cheng ,  LIN, Meng-Han ,  WANG, Sheng-chen ,  CHIA, Han-Jong ,  LIN, Chung-Te

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  H01L21/28 ,  H01L29/78

摘要： In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：EP3945585A1

公开(公告)日：2022-02-02

申请号：EP21188617.1

申请日：2021-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： LIN, Meng-Han ,  CHIA, Han-Jong ,  WANG, Sheng-Chen ,  YANG, Feng-Cheng ,  LIN, Yu-Ming ,  LIN, Chung-Te

IPC分类号： H01L27/11597 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

摘要： In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：EP3945582A1

公开(公告)日：2022-02-02

申请号：EP21188619.7

申请日：2021-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： LIN, Meng-Han ,  CHIA, Han-Jong ,  WANG, Sheng-Chen ,  YANG, Feng-Cheng ,  LIN, Yu-Ming ,  LIN, Chung-Te

IPC分类号： H01L27/11551 ,  H01L27/11578

摘要： Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.