公开(公告)号：EP2124342A1

公开(公告)日：2009-11-25

申请号：EP08711039.1

申请日：2008-02-08

申请人： Thine Electronics, Inc.

发明人： SUGANO, Takayuki ,  YATSUDA, Senichiro ,  OHTSUKA, Shigeki ,  CHIBA, Yutaka

IPC分类号： H03L7/107 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183

摘要： A PLL frequency synthesizer 1 according to one embodiment of the present invention is provided with a frequency divider 30, a phase comparator 40, a charge pump 50, a loop filter 60, a voltage controlled oscillator 70, and a changeover switch (within the switching unit 80). The loop filter 60 has a reference potential on a semiconductor substrate as a ground potential, and the changeover switch is formed on the semiconductor substrate 2 and switches connection between an intermediate node of the loop filter 60 and the reference potential on the semiconductor substrate 2 to switch the time constant of the loop filter 60.

摘要翻译： 根据本发明的一个实施例的PLL频率合成器1具有分频器30，相位比较器40，电荷泵50，环路滤波器60，压控振荡器70和转换开关（在开关 单位80）。 环路滤波器60在半导体衬底上具有作为接地电位的参考电位，并且转换开关形成在半导体衬底2上，并且将环路滤波器60的中间节点与半导体衬底2上的参考电位之间的连接切换到 切换环路滤波器60的时间常数。