Undersampled clock signal synchronization aid device and device for reconstructing undersampled clock signals, for a packet-switched network
    1.
    发明公开
    Undersampled clock signal synchronization aid device and device for reconstructing undersampled clock signals, for a packet-switched network 有权
    用于同步的时钟信号中的辅助设备二次采样,及对被分组欠时钟信号的再生装置交换网络

    公开(公告)号:EP1956738A1

    公开(公告)日:2008-08-13

    申请号:EP08101270.0

    申请日:2008-02-04

    IPC分类号: H04J3/06 H04L7/04

    摘要: A synchronization aid device (D2) is part of receiving communication equipment (EQ2) of an IP network, having a primary clock signal consisting of primary clock pulses spaced apart by a first period. This device (D2) comprises i) a counter (C2) required to increment its value by one unit on each primary clock pulse and reset its value to zero each time it reaches a value M, ii) detection means (MD2) required to generate a secondary clock pulse each time the value of the counter (C2) is zero, the secondary clock pulses forming a secondary clock signal having a second period equal to M times the first period, and iii) control means (MC2) required, each time the receiving equipment (EQ2) receives a packet containing at least one first bit having a first value, to initialize the counter (C2) with a chosen value.

    摘要翻译: 一个同步辅助设备(D2)是接收到IP网络的通信设备(EQ2),具有主时钟信号由被第一周期分隔开的主时钟脉冲的一部分。 此设备(D2)包括i)计数器(C2)需要由一个单元上的每个主时钟脉冲来递增其值和复位它的值在每次到达值M时为零,ⅱ)检测装置(MD2)需要产生 每次计数器的值(C2)第二个时钟脉冲是零,辅助时钟脉冲形成具有第二周期等于M倍的第一周期的第二个时钟信号,以及iii)控制装置(MC2)需要,每次 所述接收设备(EQ2)接收到包含具有第一值的至少一个第一比特,与所选择的值来初始化计数器(C2)的分组。