公开(公告)号：EP0771490B1

公开(公告)日：2001-05-02

申请号：EP96914667.9

申请日：1996-05-16

申请人： VLSI TECHNOLOGY, INC. ,  Arcus, Christopher A. ,  Bhushan, Bharat ,  Ta, Paul D.

发明人： ARCUS, Christopher, A. ,  BHUSHAN, Bharat ,  TA, Paul, D.

IPC分类号： H03K3/0231 ,  H03L7/099

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages (132-140). The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN-terminal. The drain terminal of MOS transistor M4 provides an OUT- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

公开(公告)号：EP0771491A1

公开(公告)日：1997-05-07

申请号：EP96920258.0

申请日：1996-05-16

申请人： VLSI TECHNOLOGY, INC. ,  Bhushan, Bharat ,  Arcus, Christopher A. ,  Ta, Paul D.

发明人： BHUSHAN, Bharat ,  ARCUS, Christopher, A. ,  TA, Paul, D.

IPC分类号： H03K3 ,  H03L7

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

公开(公告)号：EP0771490A1

公开(公告)日：1997-05-07

申请号：EP96914667.0

申请日：1996-05-16

申请人： VLSI TECHNOLOGY, INC. ,  Arcus, Christopher A. ,  Bhushan, Bharat ,  Ta, Paul D.

发明人： ARCUS, Christopher, A. ,  BHUSHAN, Bharat ,  TA, Paul, D.

IPC分类号： H03K3 ,  H03L7

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages (132-140). The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN-terminal. The drain terminal of MOS transistor M4 provides an OUT- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

公开(公告)号：EP0771491B1

公开(公告)日：2001-05-02

申请号：EP96920258.9

申请日：1996-05-16

申请人： VLSI TECHNOLOGY, INC.

发明人： BHUSHAN, Bharat ,  ARCUS, Christopher, A. ,  TA, Paul, D.

IPC分类号： H03K3/0231 ,  H03L7/099

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.