公开(公告)号：EP0070620A3

公开(公告)日：1985-11-06

申请号：EP82302994

申请日：1982-06-10

申请人： XEROX CORPORATION

发明人： Kadekodi, Narayan K. ,  Ibrahim, Abd-El-Fattah A. ,  Handy, Roland J. ,  Tandon, Jagdish C. ,  Stoffel, James C. ,  Seachman, Ned J.

IPC分类号： H01L27/14

CPC分类号： H04N1/02805 ,  H04N1/03 ,  H04N1/0308 ,  H04N1/1932 ,  H04N1/19505 ,  H04N1/19515 ,  H04N1/19573 ,  H04N5/3692

摘要： photosensor array (28) includes two adjacent and parallel rows (30, 32) of photosensors deposited on a common substrate, the photosensors being spaced apart uniformly, with the two rows being staggered longitudinally by half a spacing so that light which would fall on the boundary between two sensors in one row falls directly on a sensor in the other row.

公开(公告)号：EP0070620A2

公开(公告)日：1983-01-26

申请号：EP82302994.7

申请日：1982-06-10

申请人： XEROX CORPORATION

发明人： Kadekodi, Narayan K. ,  Ibrahim, Abd-El-Fattah A. ,  Handy, Roland J. ,  Tandon, Jagdish C. ,  Stoffel, James C. ,  Seachman, Ned J.

IPC分类号： H01L27/14

CPC分类号： H04N1/02805 ,  H04N1/03 ,  H04N1/0308 ,  H04N1/1932 ,  H04N1/19505 ,  H04N1/19515 ,  H04N1/19573 ,  H04N5/3692

摘要： photosensor array (28) includes two adjacent and parallel rows (30, 32) of photosensors deposited on a common substrate, the photosensors being spaced apart uniformly, with the two rows being staggered longitudinally by half a spacing so that light which would fall on the boundary between two sensors in one row falls directly on a sensor in the other row.

摘要翻译： 光电传感器阵列（28）包括沉积在公共衬底上的光电传感器的两个相邻和平行的行（30,32），光电传感器被均匀间隔开，两行纵向交错一半间隔，使得将落在 一行中的两个传感器之间的边界直接落在另一行的传感器上。

公开(公告)号：EP0006717B1

公开(公告)日：1982-07-14

申请号：EP79301140.4

申请日：1979-06-14

申请人： XEROX CORPORATION

发明人： Handy, Roland J.

IPC分类号： H03K13/02 ,  G01R19/165

CPC分类号： G01R19/17 ,  G01R19/16519 ,  H03M1/34

公开(公告)号：EP0006717A1

公开(公告)日：1980-01-09

申请号：EP79301140.4

申请日：1979-06-14

申请人： XEROX CORPORATION

发明人： Handy, Roland J.

IPC分类号： H03K13/02 ,  G01R19/165

CPC分类号： G01R19/17 ,  G01R19/16519 ,  H03M1/34

摘要： An analog to digital converter as implemented by large scale integrated circuit techniques utilizing charge coupled device technology. On a single integrated circuit chip, the necessary gate and charge packet transfer paths form a cell which carries out analog to digital conversion. Depending on the amount of charge transferred from one location to the next two outputs of the cell denote digital voltage levels indicative of logic 0 or logic 1.
Utilizing a plurality of the analog to digital converter cells with transfer gates on a single integrated circuit chip, a mufti-bit AID conversion register is constructed. Digital voltage levels indicative of logic 0's or logic 1's are generated from varying analog charge levels applied.

摘要翻译： 一种使用电荷耦合器件技术的大规模集成电路技术实现的模数转换器。 在单个集成电路芯片上，必需的栅极和电荷分组传输路径形成一个执行模数转换的单元。 取决于从一个位置传送到下一个单元的两个输出的电荷量表示表示逻辑0或逻辑1的数字电压电平。在单个集成电路芯片上利用具有传输门的多个模数转换器单元， 构建了一个多位A / D转换寄存器。 指示逻辑0或逻辑1的数字电压电平由应用的变化的模拟充电电平产生。