公开(公告)号：EP0713681A4

公开(公告)日：1999-12-08

申请号：EP95918181

申请日：1995-05-11

申请人： YOKOGAWA MEDICAL SYST

发明人： SUZUKI YOICHI

IPC分类号： A61B8/00 ,  G01S7/52 ,  H04J11/00

CPC分类号： G01S7/52028 ,  G01S7/52025

摘要： Phased signals of multiple channels are added without sampling clocks of multiple phases, and the limit to the frequency of a reference wave is reduced even at a constant sampling rate. The multichannel digital receiving device comprises a probe (2) which receives ultrasonic echo signals and outputs analog reception signals through multiple channels, A/D converters (31-3x), delay circuits (41-4x) which are respectively provided for the channels and delay digital data by prescribed delay time, digital quadrature detecting circuits (61-6x) which perform digital quadrature detection of delayed digital data and extract channel in-phase components and channel quadrature components, an adder circuit (71) which adds the channel in-phase components and outputs a synthesized in-phase component, and another adder circuit (7Q) which adds the channel quadrature components and outputs a synthesized quadrature component (7Q).

摘要翻译： 多个信道的相位的信号而没有取样多相位的时钟，并将该限制到参考波的频率，即使在恒定的采样速率被降低。 多信道数字接收装置包括探头（2），通过分别设置为哪个频道和多个信道，A / D转换器（31-3x），延迟电路（41-4x）接收超声回波信号并输出​​模拟接收信号 由规定的延迟时间的延迟的数字数据，数字正交检测电路（61-6x）哪个执行延迟的数字数据的数字正交检波，提取信道的同相分量和正交分量信道到加法器电路（71），其中增加的信道IN- 相分量和输出合成的同相分量，并且这增加了信道的正交分量，并输出一个合成正交分量（7Q）另一加法器电路（7Q）。

公开(公告)号：EP0639347A4

公开(公告)日：1996-01-17

申请号：EP93901550

申请日：1993-01-13

申请人： YOKOGAWA MEDICAL SYST

发明人： AMEMIYA SHINICHI ,  SUZUKI YOICHI

IPC分类号： A61B8/00 ,  G01N29/44 ,  G01S7/52 ,  H03H11/16 ,  H03H17/08

CPC分类号： G01S7/52046 ,  H03H17/08

摘要： A digital phase shifter capable of shifting the phases of data row by steps shorter than the sampling period even though the sampling signal the phase of which is fixed or a clock signal is used. This phase shifter comprises: a memory for storing consecutively time series data sampled at given periods in addresses corresponding to the sampling times; reading means for reading from this memory consecutively the data at sampling times earlier than the current sampling time by a desired period of time in synchronism with the sampling of the time series data; a register for holding several consecutive pieces of data including the latest one with respect to those read from the memory; and means for generating interpolated data in desired divided positions at the sampling intervals of a plurality of pieces of data held in this register by adding weights to the plural pieces of data held in it.