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87 条记录 (耗时 0.013 秒)

    Communication equipment realizing easy communication between apparatus
    1.
    发明公开
    Communication equipment realizing easy communication between apparatus 审中-公开
    用于设备之间容易通信传输设备

    公开(公告)号：EP1069732A3

    公开(公告)日：2003-04-16

    申请号：EP00115154.7

    申请日：2000-07-12

    申请人： Yozan Inc.

    发明人： Takatori, Sunao, c/o Yozan Inc. ,  Yamamoto, Makoto

    IPC分类号： H04L12/40 ,  H04Q9/00

    CPC分类号： H04L29/12254 ,  H04B3/542 ,  H04B2203/5445 ,  H04L12/28 ,  H04L29/12839 ,  H04L61/2038 ,  H04L61/6022 ,  H04Q9/14

    摘要： Power supply sockets of a distributing system of interior power supply wiring are provided with a communication distributing terminal, and apparatus (A1-An) are provided with a terminal unit 2 for connection to a communication line CL. A unique address is assigned for the terminal unit 2. A communication line CL is provided with a timing clock supply line TL, a unique address communication line AL, and a local area network (LAN) line LL, thereby connecting the apparatus (A1-An) connected to the power supply socket to the communication line CL. The unique address of the terminal unit 2 connected to the communication line CL is transmitted to the unique address communication line AL, and communication with the terminal unit 2 is controlled through the LAN line LL by the communication control unit 1. The terminal unit 2 transmits its own unique address to the unique address transmission line AL during a predetermined address registration period, when it failed to find its own unique address in unique addresses transmitted from the communication control unit 1. Thereby realizes very easy communication between the apparatus (A1-An).

    Acquisition and tracking filter for spread spectrum signals
    2.
    发明公开
    Acquisition and tracking filter for spread spectrum signals 失效
    Erfassungs- und VerfolgungsfilterfürSpreizspektrumsignale

    公开(公告)号：EP0757450A3

    公开(公告)日：2000-06-21

    申请号：EP96112313.0

    申请日：1996-07-30

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H04B1/707

    CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

    摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

    摘要翻译： 本发明的目的是提供一种与传统电路相比大大降低电力消耗的滤波器电路，以及以足够高的速度实现第一次采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器，第一采集和保持由匹配滤波器执行，相关操作由滑动相关器执行，并且停止电压以供应 到匹配的过滤器。

    Multiplication circuit
    5.
    发明公开
    Multiplication circuit 失效
    Multiplizierschaltung

    公开(公告)号：EP0786733A2

    公开(公告)日：1997-07-30

    申请号：EP97101295.0

    申请日：1997-01-28

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Takatori, Sunao ,  Yamamoto, Makoto

    IPC分类号： G06J1/00

    CPC分类号： G06J1/00

    摘要： Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X i corresponding to each clement of the first input data string is input to capacitance switching circuits 10 1 to 10 n through input terminals 1 1 to 1 n . m bit of digital control data A i corresponding to each element of the second input data string are input to each capacitance switching circuit 10 i , and each bit a j of the control signal A j is input to the corresponding multiplexer circuit 6 ij . In the multiplexer circuit 6 ij , the capacitances C ij corresponding to the value of each bit of the control signal a j are connected to the input terminal 1 i or the reference charge V STD . The voltages corresponding to the products of inputted analog voltages X i and the control signals A i are outputted from each capacitance switching circuit 10 i . The output voltages of each capacitance switching circuit 10 i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

    摘要翻译： 执行乘法，包括通过少量硬件高速累积。 对应于第一输入数据串的每个部分的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在多路复用器电路6ij中，与控制信号aj的每个位的值对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10i输出与输入的模拟电压Xi和控制信号Ai的乘积对应的电压。 每个电容切换电路10i的输出电压被并联地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。

    Memory device
    8.
    发明公开
    Memory device 失效

    公开(公告)号：EP0584688A3

    公开(公告)日：1994-04-06

    申请号：EP93113106.4

    申请日：1993-08-16

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

    IPC分类号： G11C11/412

    CPC分类号： G11C11/412

    摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size. The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
       iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

    Memory device
    9.
    发明公开
    Memory device 失效
    存储设备

    公开(公告)号：EP0584688A2

    公开(公告)日：1994-03-02

    申请号：EP93113106.4

    申请日：1993-08-16

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

    IPC分类号： G11C11/412

    CPC分类号： G11C11/412

    摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.
    The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
       iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

    摘要翻译： 本发明的一个目的是提供一种不需要刷新，其电路尺寸小的存储器件。 该存储器件具有一个存储单元“MC”，该存储单元包括：i）具有通过保护电阻“R1”接地的输入电压“Vi”和源“S1”接地的栅极“G1”的P沟道第一FET; ii）具有连接到第一FET的漏极“D1”的栅极“G2”，连接到电源“Vcc”的漏极“D2”和连接到栅极的源极“S2”的N沟道的第二FET 第一个FET的“G1”通过保护电阻“R2”; 和iii）连接第二FET的栅极“G2”和电源“Vcc”的开关“SWR”。 自保持电路由一对FET形成。

    A learning method for a data processing system
    10.
    发明公开
    A learning method for a data processing system 失效
    LernverfahrenfürDatenverarbeitungsanlage。

    公开(公告)号：EP0450521A2

    公开(公告)日：1991-10-09

    申请号：EP91105033.4

    申请日：1991-03-28

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Takatori, Sunao ,  Yamamoto, Makoto

    IPC分类号： G06F15/80

    CPC分类号： G06N3/082

    摘要： A learning method for a data processing system comprising an input layer and output layer which comprises a plurality of neurons each of which outputs an predetermined data after igniting according to the predetermined processing results performed onto an input data, and an middle layer, arranged between the input and output layer, the middle layer comprising a plurality of neurons each of which is connected to each neuron of the input and output layer; characterized in the following steps: the ignition patterns of the input layer and the output layer are determined artificially according to a plurality of inputs and outputs; weights of synapses of the middle layer and the output layer are increased so as to obtain the tendency that the ignition pattern of middle layer becomes the nearest approximation to the ignition patterns of input layer and output layer according to each input and output; the same processings as above are performed with respect to all inputs and outputs.

    摘要翻译： 一种用于数据处理系统的学习方法，包括输入层和输出层，其包括多个神经元，每个神经元根据对输入数据执行的预定处理结果在点燃之后输出预定数据，以及中间层，布置在 输入和输出层，中间层包括多个神经元，每个神经元连接到输入和输出层的每个神经元; 其特征在于以下步骤：根据多个输入和输出人工确定输入层和输出层的点火模式; 中间层和输出层的突触重量增加，以获得根据每个输入和输出中间层的点火模式与输入层和输出层的点火模式近似近似的趋势; 对于所有输入和输出执行与上述相同的处理。