公开(公告)号：EP1241817A1

公开(公告)日：2002-09-18

申请号：EP01972710.6

申请日：2001-10-05

申请人： Yozan Inc.

发明人： ZHOU, Changming, c/o YOZAN INC. ,  CHEN, Xiao Yuan, c/o YOZAN INC. ,  SUZUKI, Kunihiko, c/o YOZAN INC.

IPC分类号： H04J13/04

CPC分类号： H04B1/7073 ,  H04B1/7095

摘要： A 3-step cell search type receiver apparatus with an improved accuracy is provided. The receiver apparatus comprises a matched filter MF and sliding correlator unit SC to which a reception signal Sin is inputted. The matched filter MF computes correlation between the reception signal Sin and a primary synchronization code PSC and produces an output Spsc, which is retained in a memory MEM1 and then processed by a timing detection unit TDP. The sliding correlator unit SC comprises a plurality of sliding correlators SC1 to SCq, whose outputs A [1] to A [q] are retained in a memory MEM2 and then processed by a timing group identification unit TGI. The sliding correlator unit SC computes correlation based on the primary and secondary synchronization codes or the secondary synchronization code. In the former case, inphase-addition is performed after performing channel estimation and phase correction, and in the latter case, only inphase-correction is performed.

摘要翻译： 提供了具有改进的精确度的三步骤小区搜索类型接收机装置。 接收器装置包括匹配滤波器MF和滑动相关器单元SC，接收信号Sin被输入到滑动相关器单元SC。 匹配滤波器MF计算接收信号Sin与主同步码PSC之间的相关性，并产生输出Spsc，输出Spsc保存在存储器MEM1中，然后由定时检测单元TDP处理。 滑动相关器单元SC包括多个滑动相关器SC1至SCq，其输出A [1]至A [q]保留在存储器MEM2中，然后由定时组识别单元TGI处理。 滑动相关器单元SC基于主同步码和辅助同步码或辅同步码来计算相关性。 在前一种情况下，在执行信道估计和相位校正之后执行同相相加，而在后一种情况下，仅执行同相校正。

公开(公告)号：EP1353449A1

公开(公告)日：2003-10-15

申请号：EP02715780.9

申请日：2002-01-17

申请人： Yozan Inc.

发明人： SUZUKI, Kunihiko, c/o YOZAN INC. ,  CHEN, Xiao Yuan, c/o YOZAN INC. ,  ZHOU, Chang Ming, c/o YOZAN INC.

IPC分类号： H04B1/707 ,  H04Q7/38

CPC分类号： H04B1/7113 ,  H04B1/7117 ,  H04B7/0613 ,  H04B2201/70701

摘要： By calculating the complex product between each of the complex conjugate pattern for the pilot patterns assigned individually to a plurality of transmitting antennas of a base station and de-spread signals (ISI, ISQ), which have been obtained from a received signal by de-spreading portion (22), a separating section (23) separates the pilot block of the de-spread signals, for each of the plurality of transmitting antennas, from the received signal. Subsequently, after a delay profile for the transmitted signal from each of the plurality of transmitting antennas is generated by using the separated signals (PLI 1 , PLQ 1 ), (PLI 2 , PLQ 2 ), a delay profile combining portion (27) combines into a delay-profile for multi-path selection, and multi-path selection is performed based on the delay profile for multi-path selection. Therefore, highly accurate path search is possible in a DS-CDMA system that employs a transmitter diversity scheme.

摘要翻译： 通过计算用于分别分配给基站的多个发射天线的导频模式的复共轭模式中的每一个和通过解除接收信号从接收信号获得的解扩信号（ISI，ISQ）的复乘积， 扩展部分（22），分离部分（23）从所接收的信号中分离出多个发射天线中的每一个的解扩信号的导频块。 随后，在通过使用分离信号（PLI1，PLQ1），（PLI2，PLQ2）产生来自多个发送天线中的每一个的发送信号的延迟曲线之后，延迟分布组合部分（27） 用于多路径选择的简档，并且基于用于多路径选择的延迟分布来执行多路径选择。 因此，在采用发射机分集方案的DS-CDMA系统中，高精度的路径搜索是可能的。

公开(公告)号：EP1286466A1

公开(公告)日：2003-02-26

申请号：EP01930149.8

申请日：2001-05-15

申请人： Yozan Inc.

发明人： SUZUKI, Kunihiko, c/o YOZAN INC. ,  ZHOU, Changming, c/o YOZAN INC.

IPC分类号： H03H17/00 ,  H04J13/00 ,  G06F17/10

CPC分类号： H03H17/0254

摘要： The present invention provides a matched filter circuit, which has a small circuit scale, and can save power. An after-stage section of the matched filter circuit has n hold circuit groups H21, H22, ... H2n connected with an output signal Dout1(i) of a pre-stage section in parallel, and the output of each hold circuit groups H21 to H2n is connected individually to each multiplier M21, M22, ... M2n. Each multiplier multiplies the output of each hold circuit group H21 to H2m by each multiplier d21, d22, ... d2m. The output of each multiplier circuit M21 to M2n is inputted to an adder circuit ADD2, and then, the total sum Dout2 (correlation output) is calculated.

摘要翻译： 本发明提供一种匹配滤波电路，其具有小的电路规模，并且可以节省功率。 匹配滤波器电路的后级部分具有与并联的前级段的输出信号Dout1（i）连接的n个保持电路组H21，H22，... H2n，并且每个保持电路组H21的输出 到H2n分别连接到每个乘法器M21，M22，... M2n。 每个乘法器将每个保持电路组H21的输出乘以每个乘法器d21，d22，... d2m。 每个乘法器电路M21至M2n的输出被输入到加法器电路ADD2，然后计算总和Dout2（相关输出）。